Hitachi, Ltd.

Hidetaka Aoki

Takeki Yazaki

Yuji Tsushima

Michitaka Okuno

Shinji Nishimura

Yuji Ogata

Tomohiro Nakamura

Koichi Takayama

In a distributed information communication processing system in which a plurality of information communication devices provides a service through a network, response speed, electric power consumption, and further reliability are improved. The distributed information communication processing system which provides various services is configured by associating an entrance node (EN) which executes filtering near sensors, actuators, and terminals being information sources, an intelligent node (IN) which changes an information processing position and executes information processing and communication processing instead of a data center (DC), and a management node (MN) which manages these nodes. Thereby, real time type information processing can be realized.

Information and communication processing system, method, and network node

A system permitting alteration of the information processing position, where an existing information system is used, while minimizing alterations in configuration or the like, is to be provided. Intelligent nodes each having an information processing section and any desired address altering section are arranged on boundaries of a network where packets are likely to pass. This node has a flow table for recognizing as a flow a group of packets transmitted from each user's terminal, a flow status table for determining the connection state and the next destination address or the final destination address of each flow, and a module to observe the loaded state of its own information processing function. It rewrites the destination address of any flow not in a connection-established state in the flow status table to a less loaded one out of its own information processing function section or external information processing apparatus.

Distributed router computing at network nodes

Barrier synchronization between multiprocessors is performed at high speed while reducing overhead of parallel processing without adding any special hardware mechanism. A parallel computer synchronization method is provided to synchronize threads through barrier synchronization for parallel execution of plural threads on plural processor modules. The parallel computer has plural processor modules (Pand P) equipped with plural processor cores (cputo cpu). The processor cores are each assigned plural threads (Thto Th) to execute multithread processing. The plural threads (Thto Th) are set in hierarchical groups (Gr), and barrier synchronization is performed on each group separately.

Synchronization method and program for a parallel computer

Disclosed is a memory system which comprises a first cache memory of a high rank close to a processor; a second cache memory or a main memory device of a lower rank; a first table for storing a line address when there is no line data in the first cache memory at a time of making a transfer request for the line data and the transfer request for the line data is made to the second cache memory or the main memory device; and means for comparing a line address registered in the first table with a line address of a transfer destination every time the transfer request is made. When a result of comparison of the line address in the first table is a miss-hit, the line address of the transfer destination is registered in the first table and it is indicated whether the result of comparison of the line address in the first table is a hit or miss-hit.

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Tokyo, Japan

Hidetaka Aoki