Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Socionext Inc.

Panasonic Intellectual Property Management Co., Ltd.

Hideshi Nishida

Tokuzo Kiyohara

Kozo Kimura

Tetsuya Tanaka

Takeshi Tanaka

Nobuo Higaki

Hiroshi Kadota

Kunihiko Hayashi

Makoto Hirai

Kazuya Furukawa

Kosuke Yoshioka

Kazushi Kurata

Shigeki Fujii

Toshio Sugimura

Takeshi Furuta

Taketo Heishi

Masaki Maeda

Hajime Ogawa

Hiroyuki Morishita

Kouji Nakajima

Hazuki Okabayashi

Takahiro Kageyama

Toshiaki Tsuji

Tomonori Kataoka

Ryuji Matsuura

Shuji Miyasaka

Masato Suzuki

Takaharu Tanaka

Satoshi Takashima

Tetsuji Mochida

Tsuneyuki Suzuki

Kouzou Kimura

Hiroyuki Oka

Akira Miyoshi

Yutaka Tanaka

Yoshiyuki Wada

Masashi Hoshino

Yorihiko Wakayama

Manabu Kuroda

Yoshihiro Koga

Toshiyuki Ochiai

Atsushi Ito

Yukiharu Ieda

Yosuke Furukawa

A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.

Signal-processing apparatus including a second processor that, after receiving an instruction from a first processor, independantly controls a second data processing unit without further instruction from the first processor

Signal-processing apparatus including a second processor that, after receiving an instruction from a first processor, independantly controls a second data processing unit without further instrcuction from the first processor

A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot.

Processor and program execution method capable of efficient program execution

A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src, src, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

Very-long instruction word (VLIW) processor and compiler for executing instructions in parallel

A rendering device provides improved rendering responsiveness in multi-window display for rendering scenarios in which display sizes of images vary over time, while also reducing required memory bandwidth. The device comprises: a scenario processorfor interpreting a rendering scenario and calculating for each frame period a scale-down ratio for each of a plurality of pictures; a plurality of decodersfor decoding encoded data of a plurality of videos; a plurality of first scalers for scaling-down the decoded pictures using the scale-down ratios calculated by the scenario processor; a memoryfor storing the scaled-down pictures; a plurality of second scalersfor reading the scaled-down pictures from the memory and re-scaling the scaled-down pictures to match the scale-down ratios calculated by the scenario processor for a current frame period; and, a composing unitfor composing the re-scaled pictures.

Rendering device and rendering method

Very long instruction word (VLIW) computer having efficient instruction code format

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

The present invention provides an information processing apparatus and an integrated circuit which realize parallel execution of different processing systems, and which do not require the provision of a dedicated memory storing instructions for common processing The information processing apparatus comprises: a plurality of processor elements; an instruction memory storing a first program and a second program; and an arbiter interposed between the processor elements and the instruction memory, the arbiter receiving, from each of the processor elements, a request for an instruction, from among instructions included in the first program and the second program, and controlling access to the instruction memory by the processor elements, wherein the arbiter arbitrates requests made by the processor elements when the requests are (i) simultaneous requests for different instructions included in one of the first program and the second program or (ii) simultaneous requests for an instruction included in the first program and an instruction included in the second program, and when two or more of the processor elements simultaneously request a same instruction included in one of the first program and the second program, the arbiter, when judging that the instruction memory is available to the two or more processor elements, outputs the same instruction to the two or more processor elements.

Processor with arbiter sending simultaneously requested instructions from processing elements in SIMD / MIMD modes

An arithmetic processing apparatus capable of performing an arithmetic operation for generating a condition flag commonly referred to by using a condition flag generated on an arithmetic operation unit basis in as few steps as possible is provided. The arithmetic processing apparatus, which processes multiple data in parallel based on single instruction, includes: processing elements capable of performing a common arithmetic operation based on the evaluation result of the instruction stored in the instruction register; and a condition flag arithmetic operation unit capable of performing one of the logical operation and the comparison operation on the condition flag retained in each processing element, transferring the operation result to each processing element, and updating the condition flag based on the operation result.

Arithmetic processing apparatus

An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.

Information processing apparatus and exception control circuit

An image encoding device encodes moving pictures, a moving picture count acquisition unit acquires a moving picture count of encoding target moving pictures corresponding to an arbitrary number of input moving pictures, a moving picture acquisition unit acquires one or plural encoding target moving pictures, a processing method designation unit, in accordance with the acquired count, designates processing methods relating to encoding processing that affect a computation amount, and an encoding processing unit performs encoding processing with respect to the acquired one or plural moving pictures, using time division when the plural moving pictures are plural. The encoding unit performs encoding processing using the designated methods.

Image encoding device that encodes an arbitrary number of moving pictures

A processor according to the present invention cyclically executes a plurality of threads, for each time period allocated thereto. The processor stores, for each thread, configuration information of operation cells. Each of the threads (i) causes the execution of a different predetermined number of operation cells in series, and successively reconfigures an operation cell that has completed a last operation thereof in the time period allocated to a current thread, based on a stored piece of configuration information of the operation cell that corresponds to a next thread, and (ii) causes concurrent execution of an operation cell having a configuration for the current thread and an operation cell having a configuration for the next thread.

Multi thread processor having dynamic reconfiguration logic circuit

An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor a data processing unit that performs a particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue to the processor an interrupt request to execute an exception handler.

Growing community of inventors

Nishinomiya, Japan

Hideshi Nishida