Mitsubishi Denki Kabushiki Kaisha

Hideshi Miyatake

Masaki Kumanoya

Hideto Hidaka

Katsumi Dosaka

Kazuyasu Fujishima

Yasuhiro Konishi

Hiroyuki Yamasaki

Tsutomu Yoshihara

Yuto Ikeda

Kazuhiro Shimotori

Kazuhiro Tsukamoto

Hideyuki Ozaki

Masaki Shimoda

Yoshio Matsuda

Shuji Murakami

Shigeru Mori

Michihiro Yamada

Yasumasa Nishimura

Konishi Yasuhiro

Ryouji Fukuhama

Masahiro Tomisato

Ryoji Fukuhama

A memory circuit incorporating a current-mirror type amplifier which directly amplifies a varied potential of a pair of bit lines. As soon as the word line goes High, the current-mirror type amplifier is simultaneously activated to amplify a minimal difference (100 mV) of potential between these bit lines. Data signal outputted from the current-mirror type amplifier is then transmitted to a read-only signal line. As a result, data is quickly read out before a built-in sense amplifier completes amplification, thus quickly achieving an accessing operation at extremely fast speed.

Memory circuit

A dynamic random access memory (DRAM) having a plurality of word lines and a plurality of bit line pairs comprises circuitry for applying an equalizing potential to either one or the other bit line of the paired bit lines to equalize (1) a first difference between a first potential and a second potential and (2) a second difference between the first potential and a third potential, for balanced read out of the paired bit lines. The first potential appears on a reference bit line paired with a bit line connected to a memory cell selected by an external address prior to sensing thereof, the second potential appears on the bit line when the selected memory cell contains 'H' level data and the third potential appears on the bit line when the selected memory cell contains 'L' level data. Each bit line pair has circuitry for adjusting bit line potentials consisting of a pair of capacitors having their electrodes connected to respective bit lines of an associated bit line pair in a corresponding column, and a pair of dummy word lines running parallel to the plurality of word lines, connected to respective other electrodes of the pair of capacitors. When a memory cell, connected to a bit line in a bit line pair, is selected, the potential of a dummy word line capacitively coupled to the other bit line in the bit line pair is rendered active before a sense amplifier is made active for a sensing operation.

Dynamic random access memory with dummy word lines connected to bit line

Transfer transistors are connected midway on respective bit lines of a bit line pair. Memory cells are provided for a first bit line pair and a second bit line pair partitioned by the transfer transistor, and a sense amplifier is connected to the first bit line pair. When a memory cell connected to the first bit line pair is selected, the transfer transistor turns off. Therefore, the potential difference appears only on the first bit line pair, with the potentials amplified by the sense amplifier. In this state, the potential of the second bit line pair is not changed and not amplified.

Semiconductor memory device having bit lines capable of partial operation

A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal We having a shorter duration than that of the signal W at down edge of the signal W as a trigger. The output signal We of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.

Dynamic random access memory with read-write signal of shortened duration

P-type sense amplifier and N-type sense amplifier are connected to each of bit lines in a pair of bit lines respectively. N-channel MOS transistor is connected to each of the bit lines between the P-type sense amplifier and the N-type sense amplifier, and normally turned on. Each of a plurality of memory cells is connected to any of the bit lines at the side of the N-type sense amplifier from the transistor. The power source potential generated by the P-type sense amplifier is dropped by the threshold voltage of the transistor and supplied to one of the bit liens to which the memory cells are connected. The ground potential generated by the N-type sense amplifier is supplied without changing the potential to other of the bit lines. If the threshold value of the transistors to constitute the memory cells is made equal to the threshold voltage of the transistors on the bit lines, intermediate potential between the potential as 'H' level held in the memory cells and the potential as 'L' level becomes equal to the precharge potential of the bit lines, thereby unbalance of the read-out voltages can be eliminated.

Dynamic semiconductor memory device having improved voltage read-out

An input protective apparatus for a semiconductor device (Q3) comprises an MOS transistor (Q4) having a thick gate insulating film formed therein. The MOS transistor (Q4) has one active layer connected to an input terminal (11) through a second resistor element (R2) and connected to a semiconductor device (Q3) to be protected through a first resistor element (R1), and an other active layer connected to a ground terminal. The input protective apparatus is adapted such that a resistance value R.sub.1 of a first resistor element (R1) and a resistance value R.sub.2 of the second resistor element (R2) satisfy the relation R.sub.1 &gt;R.sub.2, and the on-resistance R.sub.3 of the MOS transistor (Q4) and the resistance value R.sub.2 satisfy the relation R.sub.3 &lt;&lt;R.sub.2.

Input protective apparatus of semiconductor device

A DRAM comprises equalizing capacitance for equalizing the difference between a potential on a bit line to which a selected memory cell is connected and a potential on a reference bit line paired with the bit line when the selected memory cell stores 'H' information and that when the selected memory cell stores 'L' information, before sensing operation is started. The amplitude of a potential on a selected word line is at an operating power-supply voltage Vcc level of the DRAM.

Dynamic random access memory with well-balanced read-out voltage on bit

A semiconductor dynamic random access memory is provided comprising bit line pairs divided into groups and sense amplifiers, one for each bit line pair group provided on one side of the bit line pairs in a line. When a word line is selected, only one bit line pair is released from a precharge.equalize state to be connected to a corresponding sense amplifier in each bit line pair group in accordance with address information of the word line. Memory cells are arranged such that only one memory cell is connected to the selected word line in each bit line pair group.

Semiconductor dynamic random access memory with relaxed pitch condition

A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal W having a shorter duration than that of the signal W at a down edge of the signal W as a trigger. The output signal W of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.

Dynamic random access memory

A word line driving signal generating circuit and a sense amplifier activating signal generating circuit are provided for every partitioned memory cell array. When the levels of an external RAS signal and an external CAS signal have a predetermined relation and an external RNC signal remains at a predetermined potential or more, a refresh operation is started. A refresh address is generated from a refresh address counter in a sense restore control circuit. All of the memory cell arrays are simultaneously refreshed in response to the address. On this occasion, an operation for selecting a column by a column decoder provided in each of the memory cell arrays is inhibited. In the case in which an input of the external RNC signal is not prepared, when the levels of the external RAS signal and the external CAS signal have a predetermined relation and this state is held in a predetermined time period or more, the same refresh operation as described above is started.

Block partitioned dynamic semiconductor memory device

In a DRAM device in accordance with the present invention, when a memory cell is selected for reading or writing data, at least one of the bit lines adjacent to the bit lines related with the selected memory cell is not selected simultaneously. Consequently, loss in a sense margin due to capacitance coupling between adjacent bit lines can be reduced.

Dynamic random access memory device and operating method therefor

A semiconductor memory comprises a data bit memory cell array (3), a check bit memory cell array (4), and an address decoder (19) which includes a switching circuit (20) for selectively accessing data from either the memory cell array (3) or (4). Decoding signals d.sub.l to d.sub.m are used for reading out data latched by a column address strobe (CAS) signal. The decoding signals are applied to either the memory cell array (3) or (4) through a group of switching elements selectively rendered conductive by complementary signals .phi. and .phi.. The logical values of the signals .phi. and .phi. change responsive to a change in the CAS signal state.

Semiconductor memory device having on-chip error check and correction

A semiconductor memory device such as a static RAM (Random Access Memory) device comprises a ground connection circuit of n channel field effect transistors connected between two I/O lines and the ground. The precharge circuit for precharging and the ground connection circuit both operate in response to the signal which is in synchronization with an externally applied external chip select signal. Therefore, the access delay derived from the fluctuation of the supply voltage generated before the change of the external chip select signal can be prevented.

Semiconductor memory device with improved immunity to supply voltage

A memory device provides a test mode which simultaneously carries out the function test of plural bit memory cells. In this memory device, trilevel decision is carried out based on the AND operation on the memory cell information of the selected plural bits in the single device level while bilevel decision is carried out in the board level on the basis of the OR operation on the AND result of the information of the selected plural bit memory cells and the AND result of the inverted information of the same.

Semiconductor memory device with an improved multi-bit test mode

A circuit for generating a boosted signal for a word line, coupled to a word line driving signal line for transmitting a voltage signal to the word line, coupled to a first power supply, and coupled to a second power supply for providing a voltage higher than the voltage of the first power supply, can supply a compensating voltage for the word line from the second power supply through the word line driving signal line when a voltage of the word line is decreased.

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Hyogo, Japan

Hideshi Miyatake