Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha Chiyoda-ku

Hideshi Maeno

Tokuya Osawa

Koji Nii

Tetsuo Tada

Jun Matsushima

Yoichi Maeda

Koji Shibutani

Tokuya {overscore (O)}sawa

Tatsuya Saito

Tomonori Sasaki

Hirohiko Wakasugi

Takeshi Ueki

To overcome a problem of increase of test time related to BIST in a conventional semiconductor device, a semiconductor device according to one embodiment includes a plurality of memory arrays having different sizes, a test pattern generation circuit that outputs a test pattern for the memory arrays, and a memory interface circuit that is provided for every memory array and converts an access address. The memory interface circuit shifts a test address output from the test pattern generation circuit in accordance with a shift amount set for every memory array, thereby converting the test address to an actual address of a memory array to be tested.

Semiconductor device, memory test method for semiconductor device, and test pattern generation program

An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address. A judgment circuit compares matching/non-matching of the read data and the expected value data, for each address, judges that error correction is possible when the number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC circuit, and judges that error correction is not possible when the number is not within the range.

Semiconductor device and diagnostic method therefor

There is to provide a semiconductor device capable of realizing a start time diagnosis on a non-volatile memory without any external device and any non-volatile memory out of a diagnosis target. The non-volatile memory includes an address space formed by addresses continuously read and a reservation address formed by a single or a plurality of addresses, read after the address space. A previously calculated value fixed data is stored in the reservation address. When all the data stored in the address space and the value fixed data are compressed using a predetermined initial value according to a predetermined compression algorithm, the value fixed data is the data for converging the compression value to a predetermined fixed value (for example, 0).

Semiconductor device and diagnosis method thereof

A semiconductor integrated circuit has a scan path that includes, between the output of the first logic section and the input of the functional block, a parallel path and a serial shift path for serially transferring data, and that includes first selectors for connecting the output of the first logic section or the serial shift path to the input of the functional block, and flip-flops for storing the data. The semiconductor integrated circuit further includes second selectors connected into the serial shift path of the scan path, for connecting the output of the functional block or the serial shift path to the input of the second logic section. Test data is provided from the serial shift path of the scan path to the functional block via the second selectors, and data output from the functional block is output via the second selectors after switching the second selectors.

Semiconductor integrated circuit with test circuit

32 pseudo-random numbers respectively indicated by 5 bits are successively generated in a test address generating unit, a serial output signal denoting one pair of pseudo-random numbers of 10 bits are input to 10 flip-flops serially arranged in an address shift register for each clock cycle, a read address expressed by a string of bits output from the flip-flops of odd-numbered stages is input to a read port of a RAM to perform a read test for one memory cell of the read address, and a write address expressed by a string of bits output from the flip-flops of even-numbered stages is input to a write port of the RAM to perform a write test for one memory cell of the write address. The read test and the write test for 32 memory cells are alternately performed in 64 clock cycles.

Semiconductor integrated circuit device having a test circuit of a random access memory

A semiconductor integrated circuit comprises a logic circuit to be tested by a scan test; and a scan path circuit being constituted by serially connecting a plurality of scan register circuits, each of which includes a compound gate circuit having a first logic gate and a second logic gate, a flip-flop circuit connecting an output of the compound gate circuit to a data input terminal, and a gate circuit connecting a first input thereof to a data output terminal of the flip-flop circuit and connecting a second input thereof to a second connection terminal input by a second shift mode signal, and which connects the compound gate circuit, flip-flop circuit, and gate circuit in this turn, wherein a first input of the first logic gate is connected to the logic circuit to be tested, and a second input thereof is connected to a first connection terminal input by a first shift mode signal, while a first input of the logic gate is connected to an output of the first logic gate and a second input thereof is connected to a serial input terminal.

Semiconductor integrated circuit with a scan path circuit

A semiconductor integrated circuit device with fault analysis function performs test operation for a memory circuit (such as a RAM) in which a comparison control circuit ( ) generates a comparison control signal CCMP in order to select one or more memory cells in each memory cell group ( and ) corresponding to a single bit, a specified row, a specified bit, or a specified pattern, and then outputs the comparison control signal CCMP to scan flip flops ( and ) each including a comparator ( ). The comparator ( ) performs the comparison operation between data and expected values EXP and then outputs a comparison result only when address signals are input and data are red from memory cells, as the object of test, addressed by these address signals.

Semiconductor integrated circuit device with fault analysis function

A semiconductor device comprising a memory circuit, a switch for relieving the memory circuit of its failures, and a logic circuit to be tested, facilitates a test of the logic circuit. When a switch control signal (SET) is &ldquo;1&rdquo;, for example, a switch ( ) selects predetermined 1-bit data (&equals;c) from a plurality of 1-bit data (&equals;b) outputted in parallel form from a RAM ( ) and outputs it to a logic circuit ( ), where c<b.

Semiconductor device

In a self-repairing operation, a first self-test of a RAM is performed at a first temperature to obtain a first RAM test result, a RAM built-in self-test circuit judges according to the first RAM test result that a faulty portion exists in the RAM, an LSI built-in self-repair circuit judges that the repair of the faulty portion of the RAM is possible, the LSI built-in self-repair circuit controls a redundancy control circuit to avoid the use of the faulty portion of the RAM in a normal operation, the temperature of the RAM is risen by operating the RAM or a logical circuit in a pseudo-self-test to change the first temperature to a second temperature, a second self-test of the RAM is performed at the second temperature to obtain a second RAM test result, and the LSI built-in self-repair circuit confirms that the repair of the faulty portion of the RAM is possible at each of the first and second temperatures by comparing the second RAM test result with the first RAM test result. Therefore, the reliability of the test of the RAM for the test condition change can be improved, and a correct operation of the RAM can be guaranteed at the first and second temperatures after a self-repair of the RAM.

Testing method and test apparatus in semiconductor apparatus

To provide a semiconductor integrated circuit having a redundancy-relieved data output function which can carry out a pass/fail test of a selecting operation of a redundancy-relieved output selecting circuit for redundancy-relieved output data. Data inputs D of scan flip-flops SFFC <i&plus;3>, SFFC <i&plus;2>, SFFC <i&plus;1> and SFFC <i> are connected to redundancy-relieved output data XDO <i&plus;3>, XDO <i&plus;2>, XDO <i&plus;1> and XDO <i> in place of output data DO <i&plus;3>, DO <i&plus;2>, DO <i&plus;1> and DO <i> of a conventional RAM , respectively. An AND gate receives a serial output SO <i&plus;4> at one of inputs and receives a selector test signal PFIN at the other input, and an output thereof is sent to the other input of an AND gate . AND gates to to be connected in series receive serial outputs SO <i&plus;1> to SO <i&plus;3> of the SFFC <i&plus;1> to the SFFC <i&plus;3> at inputs, respectively.

Semiconductor integrated circuit

An electronic system with a self-test function has a pseudo-random test pattern generator that serially generates data constituting a pseudo-random test pattern, and stores a 1-bit shifted pseudo-random test pattern obtained by shifting the pseudo-random test pattern by one bit. When a scan-path circuit supplies the pseudo-random test pattern to a tested circuit which carries out an operation based on the pseudo-random test pattern, and then loads an operation result of the tested circuit, the 1-bit shifted pseudo-random test pattern is supplied to the tested circuit as the next pseudo-random test pattern. This makes it possible to solve a problem of a conventional electronic system in that it takes a long time to evaluate the operation results of the tested circuit because it takes at least (1&plus;n)&times;m clock cycles, where m is the number of pseudo-random test patterns supplied to the tested circuit and n is the number of stages of the scan-path circuit.

Electronic system with self-test function and simulation circuit for electronic system

A semiconductor integrated circuit device has a redundancy circuit such that when a parallel/serial conversion circuit converts the separation information of a program element group such as one fuse element group to serial data, the serial data is transmitted through a serial/parallel conversion circuit, thus controlling circuits to be controlled such as a plurality of RAMs. Further by introducing a CRC technique in the parallel/serial conversion circuit, even when there is an error input such as cutting error of the fuse element, the information may be reproduced.

Semiconductor integrated circuit device

A semiconductor integrated circuit device includes a memory circuit and a flag generator. The memory circuit is a circuit with a test circuit and includes a redundant circuit. The flag generator loads compared result information serially output from the memory circuit, and outputs flag signals if the compared result information includes at least one piece of mismatch information. This makes it possible to solve a problem of a conventional semiconductor integrated circuit device in that it takes a long time for carrying out a fault test of bits constituting the memory circuit.

Semiconductor integrated circuit device with test circuit

When the RAM (,) is not initialized, data signals captured from the data output portions (do&lsqb;n&rsqb;) may include undefined value, but these data signals are not transferred to an MISR through the scan path (,). Transferred to the MISR are only the data signals (DI&lsqb;n&rsqb;) captured by the scan path (,). Accordingly, BIST can be applied to the combinational logic circuit (,) without requiring initialization of the RAM (,) and without being affected by undefined value. Thus, BIST to the combinational logic circuit (,) can be normally achieved in a short period.

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Tokyo, Japan

Hideshi Maeno