Seiko Instruments Inc

Ablic Inc.

Sii Semiconductor Corporation

Hideo Yoshino

Hisashi Hasegawa

Hirofumi Harada

Jun Osanai

Shinjiro Kato

Masayuki Hashitani

Keisuke Uemura

Takashi Imura

Yuichiro Kitajima

Yoshitsugu Hirose

Masahiro Hatakenaka

A semiconductor device, including: a first semiconductor element formed at a first surface on a substrate, and has a first electrode portion formed thereon a first metal silicide film; a second semiconductor element formed at a second surface at a higher position than the first surface, and has a second electrode portion formed thereon a second metal silicide film and a hydrogen supply film configured to cover a part of an upper portion of the second metal silicide film; an interlayer insulating film formed on the first semiconductor element and the second semiconductor element; a first contact hole formed through the interlayer insulating film until the first metal silicide film; a second contact hole formed through the interlayer insulating film and the hydrogen supply film until the second metal silicide film; and a metal wiring embedded in each of the first contact hole and the second contact hole.

Semiconductor device and method of manufacturing the semiconductor device

The reference voltage generation device includes a constant current circuit which includes a first MOS transistor, and a voltage generation circuit which includes a second MOS transistor. The first MOS transistor includes a gate electrode, a source region, a drain region, and a channel impurity region which have a first conductivity type and has a first channel size. The second MOS transistor includes a gate electrode of a second conductivity type, and a source region, a drain region, and a channel impurity region which have the first conductivity type and has a second channel size different from the first channel size. The channel impurity regions have different impurity concentrations.

Reference voltage generation device

A semiconductor device includes a MOS transistor and an ESD protection element comprised of an NMOS off transistor having a gate potential equal to a ground potential or a well potential. The off transistor has an N-type drain region and a P-type drain region in a drain active region thereof. The P-type region has a potential that is the potential of a P well or a P-type semiconductor substrate. A junction withstand voltage of a PN junction in the drain active region is the withstand voltage of the ESD protection element.

Semiconductor device including an ESD protection element

A reference voltage generator is constructed to be equipped with a first constant current circuit which outputs a first constant current with respect to an input voltage, a second constant current circuit which outputs a second constant current, and a voltage generation circuit which generates a voltage based on an input current, and to take a current based on the first constant current and the second constant current as an input current of the voltage generation circuit and output a reference voltage from the voltage generation circuit.

Reference voltage generator

Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.

Method of manufacturing semiconductor integrated circuit device

A semiconductor integrated circuit device has a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate. The first N-channel type high withstanding-voltage transistor includes a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor includes a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors are capable of operating at 30 V or higher and are integrated on the N-type semiconductor substrate.

Semiconductor integrated circuit device having low and high withstanding-voltage MOS transistors

A reference voltage generator has a first N type depletion MOS transistor configured to cause a constant current to flow, and a second N type depletion MOS transistor diode-connected to the first N type depletion MOS transistor and configured to generate a reference voltage based on the constant current. The first and second N type depletion MOS transistors have the same temperature coefficient of a threshold voltage. The first N type depletion MOS transistor has a buried channel into which arsenic impurities are diffused. The second N type depletion MOS transistor has a buried channel into which phosphorous impurities are diffused.

Reference voltage generator having diode-connected depletion MOS transistors with same temperature coefficient

A reference voltage generator has a depletion mode MOS transistor of a first conductivity type for supplying a constant current flow, and an enhancement mode MOS transistor of the first conductivity type having a diode connection to the depletion mode MOS transistor for generating a reference voltage based on a constant current supplied by the depletion mode MOS transistor. The enhancement mode MOS transistor has a mobility substantially equal to a mobility of the depletion mode MOS transistor such that the enhancement mode MOS transistor and the depletion mode MOS transistor have substantially equal temperature characteristics.

A reference voltage generating circuit has more than two first wells each having a first impurity concentration and more than two second wells each having a second impurity concentration different from the first impurity concentration. A first group of MOS transistors has more than two MOS transistors formed in respective ones of the first wells. A second group of MOS transistors has More than two MOS transistors formed in respective ones of the second wells.

Semiconductor reference voltage generating device

Provided is a reference voltage generation circuit that has a flat temperature characteristic even when there are fluctuations in manufacturing step. After a semiconductor manufacturing process is finished, electrical characteristics of a semiconductor device are evaluated. Temperature characteristic of each reference voltage (VREF) of three unit reference voltage generation circuits () is evaluated. Then only a unit reference voltage generation circuit () having the most flat temperature characteristics is selected from among the three unit reference voltage generation circuits (). Only fuses () of the selected unit reference voltage generation circuit () are not cut, but other fuses () are cut. Accordingly only the selected unit reference voltage generation circuit () operates, and the other unit reference voltage generation circuits () do not operate.

Reference voltage generation circuit

Provided is a manufacturing method for an offset MOS transistor capable of operating safely even under a voltage of 50 V or higher. In the offset MOS transistor which includes a LOCOS oxide film, the LOCOS oxide film formed in a periphery of a drain diffusion layer, in which a high withstanding voltage is required, is etched, and the drain diffusion layer is formed so as to spread into a surface region of a semiconductor substrate located below a region in which the LOCOS oxide film is thinned. As a result, end portions of the drain diffusion layer are covered by an offset diffusion layer, whereby electric field concentration occurring in a region of a lower portion of the drain diffusion layer can be relaxed.

Semiconductor device and manufacturing method thereof

Provided is a semiconductor device formed to an SOI substrate including a MOS transistor in which a parasitic MOS transistor is suppressed. The semiconductor device formed on the SOI substrate by employing a LOCOS process is structured such that a part of a polysilicon layer to becomes a gate electrode includes: a first conductivity type polysilicon region corresponding to a region of the silicon active layer which has a constant thickness and is to become a channel; and second conductivity type polysilicon regions corresponding to LOCOS isolation edges in each of which a thickness of the silicon active layer decreases.

Semiconductor device and method of manufacturing the same

Provided is a reference voltage circuit in which a temperature characteristic of a reference voltage is excellent and a circuit scale is small. In the reference voltage circuit, for example, a temperature correction circuit separated from the reference voltage circuit is not used and a difference voltage between threshold voltages of two E-type NMOS transistors (and) is added to a threshold voltage of a D-type NMOS transistor to generate a reference voltage (Vref). Therefore, the influence of the D-type NMOS transistor on the reference voltage (Vref), which is a degradation factor of the temperature characteristic of the reference voltage (Vref), may be reduced to suppress a change in tilt and curve of the reference voltage (Vref) with respect to a temperature.

Reference voltage circuit

A bipolar transistor for semiconductor device has a collector region having a first conductivity type disposed on a surface of a semiconductor substrate having the first conductivity type. A base region having a second conductivity type is disposed in the collector region. An emitter region having the first conductivity type is disposed in the base region. A high concentration first conductivity type region for a collector electrode is disposed in the collector region. A high concentration second conductivity type region for a base electrode is disposed in the base region. The high concentration first conductivity type region for a collector electrode and the high concentration second conductivity type region for a base electrode contact directly with each other so that the collector region and the base region have a same potential.

Growing community of inventors

Chiba, Japan

Hideo Yoshino