Fujitsu Corporation

Fujitsu Semiconductor Limited

Hideo Yamashita

Ryuji Kan

Yoshiteru Ohnuki

Tsutae Shinoda

Masayuki Kato

Toshio Yoshida

Daisuke Mizutani

Aiichiro Inoue

Iwao Yamazaki

Masateru Koide

Shizuo Andoh

Yuji Yoshida

Kazuyuki Imamura

Seiji Ueno

Yoichi Ueda

Kenji Murase

Yasukichi Okawa

Sei Sato

Tomoyuki Unotoro

Shigeharu Matsuzaki

Yasunari Shirouchi

A processor for processing data and correcting an error occurring in the data, the processor includes: a register that stores data with error check data and error correction data; an error detector that detects an error in the data stored in the register by using the error check data; and an error corrector that corrects the detected error by using the error correction data and that stores the corrected data back into the register.

Processor and error correcting method

A debugging mechanism receives arithmetic operation data inputs for causing an arithmetic unit to perform an arithmetic operation, and a control signal used for the arithmetic operation. The debugging mechanism includes a debug control unit which includes (1) a counter that performs a counting operation cyclically according to the processor clock operation, and (2) an OR circuit that receives the control signal and a counter signal that is output when the counter value becomes a specific value, and outputs an output signal generated by performing a logical OR operation of the control signal and the counter signal. The debugging mechanism also includes a debug storage unit which stores the arithmetic operation data, the counter value, and the control signal when the output of the OR circuit is valid.

Debugging mechanism having an OR circuit for triggering storage of arithmetic operation data whenever a valid control signal is received or a clock-based counter overflows

A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board.

Multi-chip module

A circuit outputs, upon receipt of data and a parity of the data, count information on the number of bits in the data represented as a base-n number (n: a natural number equal to or larger than 2) and the parity of the count information. The circuit includes a determining unit and an inverting unit. The determining unit determines that the number of bits in the data represented as a base-n number is a specific value. The inverting unit outputs, as the parity of the count information, any one of a value of the parity of the data and an inverted value of the parity depending on a result of determination by the determining unit.

Parity generation circuit, counter circuit, and counting method

A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor for a plurality of clocks; and a signal reading unit that scans and reads out a signal value stored in the register.

Processor debugging apparatus and processor debugging method

A method and an apparatus for averaging includes generating a carry using a least significant bit of each of two binary numbers, wherein the two binary numbers include a first binary number and a second binary number, and adding a first shifted binary number, a second shifted binary number, and the carry generated, thereby outputting an average of the two binary numbers. The carry generated is added to the least significant bit position. The first shifted binary number is obtained by right-shifting the first binary number by one bit, and the second shifted binary number by right-shifting the second binary number by one bit.

Method and apparatus for averaging parity protected binary numbers

The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching instruction and an instruction relating to data stored in the current register or data held in the replacing buffer; and a control unit which transfers, if a window switching instruction is decoded at execution of the window switching instruction by the arithmetic operation unit, data of the register window which is to be specified by the current window pointer upon completion of execution of the window switching instruction, to the replacing buffer.

Register window system and method that stores the next register window in a temporary buffer

In the structure of register files composed of a master register file and a working register file, when data is read, the working register file is accessed. When data is written, the both the master register file and the working register file are accessed. In the working register file, data of the current window, and data preceded thereby, and data followed thereby are stored. Thus, even if the SAVE instruction or the RESTORE instruction are successively executed, instructions can be processed out of order. As a result, the efficiency of the process is improved.

Register file in the register window system and controlling method thereof

An arithmetic processing method and arithmetic processing device each which can reduce the number of logical stages needed to obtain the final arithmetic result, thus executing an arithmetic process such as a floating-point multiplication at high speed to reduce the arithmetic process time. According to the arithmetic processing method and arithmetic processing device, the possibility that an arithmetic exception occurs in the arithmetic result obtained through an arithmetic process is judged in the middle of the arithmetic process of the dedicated arithmetic processing unit. Transmitting an arithmetic end signal to the instruction control unit is inhibited when it is judged that there is a possibility; the arithmetic process with the possibility is executed by means of another arithmetic unit different from the dedicated arithmetic unit. Thereafter the arithmetic end signal regarding the arithmetic process is transmitted to the instruction control unit. The arithmetic processing method and arithmetic processing device can be applied to the case where an arithmetic process such as a floating-point arithmetic operation is performed in a pipeline mode.

Arithmetic processing method and arithmetic processing device

An apparatus for controlling a command retry widens an applied range of a retry function in an information processor for executing a program under pipeline control and aiding reliability, availability and serviceability of the information processor. The command retry control apparatus translates an instruction contained in the program into commands in a processable form and executes the processing on a command basis. The command retry control apparatus determines, if an error occurs during the execution of the command, whether or not an operand value is a normal value and executes, when the operand value is the normal value, a command retry by stopping inputting a next command. The command retry control apparatus continues the processing by resuming the inputting of the next command when normally finishing the command retry. If the error reoccurs in the middle of the command retry, the command retry control apparatus decides that the command is unexecutable and notifies a management system of the occurrence of the error.

Apparatus/method for error detecting and retrying individual operands of

The gas discharge panel described here is an AC plasma display panel with electrodes arranged on a substrate, and the electrodes and substrate are coated with a dielectric layer for insulation from the gas filled discharge space, with an improvement in the dielectric layer surface. The improvement being an overcoat layer of at least two alkaline earth compounds, especially CaO and SrO, provided on the dielectric layer surface of this display panel. This overcoat layer significantly lowers the operating voltages of the panel.

Gas discharge panel

A first glass substrate supports a plurality of electrodes arranged in concentric circles. A second glass substrate supports a plurality of shift electrodes arranged radially. The substrates are positioned face to face with a specified space between them filled with an ionizable gas. The radially arranged shift electrodes are periodically connected to common buses each connected to a corresponding one of a plurality of shift driver circuits equal in number to the buses. At least one of the shift electrodes is selectively connected to a write driver circuit and to one of the shift driver circuits. When the one of the shift electrodes is energized by a signal from the write driver circuit, discharge spots are generated at the intersection of the one of the shift electrodes and the concentrically arranged electrodes. The discharge spots are endlessly shifted in clockwise or counterclockwise direction along the concentrically arranged electrodes through the switching of operating voltages applied sequentially to the shift electrodes from the shift driver circuits via the buses.

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Kawasaki, Japan

Hideo Yamashita