Renesas Electronics Corporation

Kokusai Denshin Denwa Kabushiki Kaisha

Sony Corporation

Nec Electronics Corporation

Kokusai Denshin Denwa Co., Ltd.

Honda Giken Kogyo Kabushiki Kaisha

Japan Polyolefins Co., Ltd.

Honda Giken Kogyo Kabushiki Kaisha Nhk Spring Co., Ltd.

Hideo Yamamoto

Kenya Kobayashi

Atsushi Kaneko

Yoshimitsu Murase

Masahiro Sueyoshi

Katsuyuki Teruyama

Yoshiaki Hirano

Yoshinori Hatori

Naofumi Hanaki

Tomohiko Nagayama

Shuichi Matsumoto

Masahiro Wada

Hirohisa Yamaguchi

Akira Honjo

Yuji Hiura

Kazuo Omori

Kitsutaro Amano

Hitomi Murakami

Kei Takehara

Hiroshi Sasaki

Koji Kinuhata

Takeshi Ogawa

Tadashi Morita

Noritoshi Takamura

Kunio Yamamoto

Atsushi Ishida

Yuichi Nagase

Kaoru Hatayama

Kosho Shibata

Kazuo Yamada

Akihiko Inooku

Taizo Fukutome

Toyoyuki Higashino

Yoshihisa Saiki

Tomio Takada

Kunihiko Asai

A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance.

Method of fabricating semiconductor device

A semiconductor device includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode housed in the trench with a gate insulator intervening, a top surface of the gate electrode being lower than a top surface of the second diffused region, a first oxide film housed in the trench and formed over the gate electrode, a second oxide film housed in the trench and formed over the first oxide film, a third oxide film housed in the trench and formed over the second oxide film, and a source electrode formed over the third oxide film and electrically connecting to the first and second diffused regions.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a semiconductor layer, a first diffused region formed in the semiconductor layer, a second diffused region formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode disposed in the trench, a top surface of the gate electrode being lower than a top surface of the semiconductor layer and sagging downwards in a center thereof, a non-doped silicate glass film disposed in the trench and formed over the gate electrode, a top surface of the silicate glass film sagging downwards in a center thereof, an oxide film disposed in the trench and formed over the non-doped silicate glass film, a top surface of the oxide film sagging downwards in a center, and a source electrode formed over the semiconductor layer so that the source electrode contacts the first and second diffusion regions, and the oxide film at the top surface thereof.

A communication device including a receiving unit, a command processing unit, an updating unit, a transmitting unit, and a selector is provided. The receiving unit receives a transmitted command. The command processing unit performs command processing in response to the received command and generates a response containing a result of the command processing. The updating unit updates information held in one area of a memory currently disabled using the result of the command processing, wherein a first area and a second area form the memory for holding information indicating a current status. The transmitting unit transmits the generated response. The selector switches the one area currently disabled and holds the information that was updated using the result of the command processing into the enabled state and the other area currently enabled into the disabled state immediately after transmission of the response is completed.

Communication device, communication method, program, and communication system

An encryption apparatus capable of effectively preventing encryption data from being illegally generated is provided. Based on apparatus identification data of an integrated circuit (IC), which is input from a computer, a secure application module (SAM) selects an encryption method from among a plurality of different encryption methods. Based on the code of the IC, the SAM selects plaintext data to be encrypted from among the plurality of different pieces of plaintext data. The SAM outputs encryption data such that the selected plaintext data is encrypted by the selected encryption method.

Encryption apparatus, program for use therewith, and method for use therewith

A semiconductor device, includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a polysilicon formed in the trench with an insulator intervening, a first oxide film formed on the polysilicon so that the first oxide film is buried in the trench, a second oxide film formed on the first oxide film so that the second oxide film is buried in the trench, and a flowable insulator film formed on the second oxide film so that the flowable insulator film is buried in the trench.

The present invention provides a vertical MOSFET which has striped trench gate structure which can secure avalanche resistance without increasing Ron. A vertical MOSFETcomprises a plurality of gate trencheswhich is arranged in stripes, an array which is sandwiched with the plurality of gate trenchesand includes Nsource regionsN+ and Pbase contact regionsP+, and a diode region (anode regionP+) which is formed so as to contact with two gate trenches. The Nsource regionsN+ and the base contact regionsP+ are alternately arranged along a longitudinal direction of the gate trench. Size of the diode region (anode regionP+) corresponds to at least one of the Nsource regionsN+ and two of the Pbase contact regionsP+.

Semiconductor device having trench gate structure

A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.

Method of manufacturing semiconductor apparatus

A data processing apparatus is provided which is capable of improving the responsiveness of communication in which only a maximum of one access request source has write authorization and the other access requests do not have write authorization when communication is performed with a plurality of access request sources. A management apparatus transmits, to a secure application module (SAM), a strong connection request requesting the obtainment of write authorization into the SAM. When it is determined that the strong connection has not already been assigned to the other management apparatuses, the SAM assigns the strong connection to the management apparatus in a state in which a weak connection having read authorization with the management apparatuses is maintained.

Data processing apparatus in which data is accessed in response to an access request from a plurality of access request sources

An epitaxial layer is formed on an n+ semiconductor substrate by epitaxial growth. A gate trench is formed to the surface of gate trench so that the bottom of gate trench reaches middle of the epitaxial layer. A gate insulator is formed on the inner wall of gate trench and a polysilicon is formed in the gate trench with the gate insulator interposed therebetween. An HTO film is formed on the surface of the polysilicon and the n&#x2212; epitaxial layer. At this time, an ion plantation is performed to the epitaxial layer through the HTO film. Hence, a p diffused base layer, an n+ diffused source layer, an n+ diffused source layer is formed. A CVD oxide film is formed on the HTO film. After a BPSG having flowability is deposited on the CVD oxide film, the BPSG film is planarized with a heat treatment of 900-1100 degree Celsius.

A MOSFET has a base layer and a source layer in a cell surrounded by a trench gate formed in a semiconductor substrate. A trench contact is formed through the source layer and the base layer. The gate is polygonal such as square. The trench contact is thin and linear so as to increase embedding characteristics. Further, the trench contact is ring or cross shaped so as to reduce a source length.

Vertical field effect transistor

Data processing apparatus, program for use therewith, and method for use therewith

A resin composition comprising: (A) a polypropylene polymer comprising a propylene/ethylene block copolymer, said polypropylene polymer having a melt flow rate of from 5 to 100 g/10 min as measured at 230.degree. C. under a load of 2.16 kg and containing components extractable with xylene at 20.degree. C., wherein the xylene-extractable components having an intrinsic viscosity as measured at 140.degree. C. in decalin of from 2.0 to 5.0 g/dl; (B) an ethylene/propylene rubber having a propylene content of from 40 to 60% by weight and a melt flow rate of from 0.5 to 10 g/10 min as measured at 230.degree. C. under a load of 2.16 kg; (C) a triblock copolymer having a melt flow rate of from more than 40 to 200 g/10 min as measured at 230.degree. C. under a load of 2.16 kg, a flat interface between said triblock copolymer and the 100.degree. C. xylene-insoluble components of said polypropylene polymer of ingredient (A) having a critical energy release rate of 20 J/m.sup.2 or higher as measured at a phase angle of from -2.degree. to -12.degree.; (D) a modified polyolefin polymer having a hydroxy group, said modified polyolefin polymer having a content of a hydroxy-containing unsaturated compound of from 0.5 to 7.0% by weight; (E) an oligomer having at least one terminal polar group, said oligomer having a number-average molecular weight of from 300 to 10,000; and (F) talc having an average particle diameter of 5 .mu.m or smaller.

Resin composition and molded object thereof

Growing community of inventors

Kanagawa, Japan

Hideo Yamamoto