Hitachi, Ltd.

Other

Hitachi Vlsi Engineering Corp.

Hideo Wada

Yasuhiro Inagami

Hiroaki Fujii

Katsumi Takeda

Hiroshi Nakamura

Teruo Tanaka

Naoki Hamanaka

Tsuyoshi Watanabe

Shigeo Takeuchi

Seiji Isogai

Hitoshi Komuro

Junji Nakagoshi

Junichi Tatezaki

Yasuhiro Sagesaka

Hiromitsu Imori

Shuichi Abe

Yasuhiro Ogata

Taturu Toba

Yoshifumi Kawamura

Mitsuyoshi Igai

Humio Goto

Katsuharu Shoda

Kisaburo Nakazawa

Atsushi Ogane

Isao Kodama

An object of the present invention is to increase efficiency in review work by appropriately narrowing down review work that verifies shapes of visual defects relating to an enormous amount of defects detected by a visual inspecting apparatus with high sensitivity. In order to appropriately extract defect information from an inspecting apparatus, a filter function and a sampling function are prepared by unitizing the functions. As a result, defects as review targets are narrowed down and extracted automatically using the filter function and the sampling function in combination. In addition, sequencing the filter conditions and the sampling conditions and registering the sequence enables automatic filtering and sampling on the basis of information on a wafer as a review target, and thereby only defect information on the review target is extracted.

Review work supporting system

An operation complete signal and a convergence result signal from each processor are transferred to the X-direction interconnection switches, AND of these signals is obtained in switch units in each interconnection switch, the signal is sent out to all the Y-direction interconnection switches through a synchronizing signal relay switch and the like in each relay switch, AND of these signals is obtained in each switch unit in the interconnection switches, and the result thereof is transferred to each processor through each synchronizing signal relay switch. With this, a logical product of an operation complete signal and a logical product of a convergence result signal from all the processors are sent in parallel to all the processors.

Parallel computing system for synchronizing processors by using partial

A data processing unit which can access a greater number of registers than registers addressable by an instruction to realize high-speed execution of a program. To this end, the data processing unit includes a greater number of floating point registers than the number of registers addressable by an ordinary instruction, a window start pointer register, a window start pointer valid register, a conversion circuit, when the window start pointer valid register has a value of 1, for converting a floating point register number in the instruction to a physical floating point register number and for changing a conversion pattern depending on the value of the window start pointer register, a window start pointer set instruction for setting a value at the window start pointer register, and floating point register pre-load and post-store instructions having a register field different in length from the ordinary instruction, and wherein the floating point register number specified by the register field is converted by the conversion circuit to the physical floating point register number on the basis of the value of the window start pointer register.

Data processing unit

A base station (5) comprises a base transmitter (6) for transmitting information optically to a plurality of portable stations (1 to 4) at such a predetermined time interval as is designated by portable station designating information. Each of the portable stations (1 to 4) comprises a potable transmitter (7) for transmitting information optically to the base station (5) in response to the transmission, which is designated by the portable station designating information coming from said base station (5), and within the range of the aforementioned time interval immediately after said transmission. Transmissions (ACK1 to ACK4) from the mating portable stations to the base station are individually inserted between the interval periods of the transmissions (REQ1 to REQ4) from the base station (5) to the portable stations (1 to 4) so that the single base station performs optical communications with the plurality of portable stations in a half-duplex time sharing manner.

Information transmitting/processing system

The data processing unit includes a greater number of physical floating point registers than the number of floating point registers accessible by an instruction, window start point register having a plurality of bits, 1-bit window start pointer valid register, conversion apparatus for converting a floating point register number in an instruction to a physical floating point register number when the value of the window start pointer valid register is 1, and changing the pattern of this conversion by a value obtained from the value of the window start pointer register or the value of a window stride designated in a specific instruction, and the value of the window start pointer register. Also provided is an instruction controller for detecting a window start pointer set instruction for setting a value to the window start pointer register, a floating point register pre-load instruction for converting the floating point register number in the instruction to a physical floating point register number by the conversion circuit from the value obtained from the value of the window start pointer register and the value of the window stride, and storing a main memory data in the physical floating point register indicated by the physical floating point register number.

Data processing unit which can access more registers than the registers

A plurality of physical registers greater in number than can be addressed by instructions are provided. The physical registers are divided into a plurality of partial groups or windows. Each of the physical registers is specified by a physical register number determined by a combination of the number of the window and a register number contained in the window. The window number is indicated by a current floating point window pointer stored in a current floating point window pointer register. In executing a vector calculation program having repetitive loops of an instruction sequence, the window is changed for each loop by changing the value of the current floating point window pointer. Vector data to be calculated at the i-th loop is read from a main memory at the loop before the i-th loop. The calculated result of the vector data at the i-th loop is stored in the main memory at the loop after the i-th loop, thereby eliminating performance degradation to be caused by a slow data read time and improving the operation speed.

Data processor with improved loop handling utilizing improved register

List operation on a vector in which the number of an element of a vector operand is represented by an element of another vector operand is to be performed with a general-purpose computer system having no vector registers. List vector elements are read out from a memory by adding at addresses determined sequentially by adding by adding values of a request vector increment register to a list vector address. A value resulting from the bit shift of the element is stored in a second operand increment register. A second vector element is read out from the memory at the address corresponding to a value resulting from addition of the content of the second operand increment register to the second operand initial address register, the element being then stored at the memory location of the address given by a value resulting from the addition of the value of the first operand vector increment register to the first operand address.

Data processing apparatus for processing list vector instructions

A computer system has a CPU, a main memory and an additional memory storage which is difficult from the main memory and an external storage. The additional storage may transmit data with the main memory and/or the CPU.

Computer system

Growing community of inventors

Hadano, Japan

Hideo Wada