Toshiba Memory Corporation

Kioxia Corporation

Hideo Wada

Takeshi Imamura

Kenichi Fujii

Osamu Matsuura

Hideki Inokuma

Genki Kawaguchi

Hajime Kaneko

Takanobu Itoh

Makoto Watanabe

Hideto Takekida

Masanari Fujita

Hiroshi Maejima

Takashi Maeda

Kenichiro Yoshii

Keisuke Nakatsuka

Tomoya Sanuki

Takaya Yamanaka

Mikiko Yagi

Masaharu Mizutani

Masanori Fujita

A semiconductor memory device includes: a stack above a peripheral circuit on a first substrate, in which first conductive layers and first insulation layers are alternately stacked in a first direction each; a first pillar through the stack, in which a semiconductor layer and each first conductive layer form a memory cell at their intersection; a second substrate including a first region above the stack and the first pillar, being connected to a semiconductor layer, and a second region juxtaposed with the first region in a second direction; a second insulation layer through the second substrate, insulating the regions from each other; and a second conductive layer including a first portion through the second substrate, and a second portion extending in the second direction above the second substrate and including a part defining a bonding pad. The second portion overlaps with the second insulation layer in the first direction.

Semiconductor memory device

A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.

According to an embodiment, a memory device comprises a conductive layer containing a metal, a semiconductor layer on the conductive layer, electrode layers stacked on the semiconductor layer in a stacking direction, a semiconductor pillar penetrating the electrode layers in the stacking direction and electrically connected to the semiconductor layer, and a charge trap layer between the electrode layers and the semiconductor pillar. The conductive layer has a recess or a through-hole below the semiconductor pillar.

Three-dimensional NAND memory device with source line comprising metallic and semiconductor layers

According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N&#x2212;2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.

Three-dimensional semiconductor memory device including slit with lateral surfaces having periodicity

A semiconductor memory device includes a substrate with a first insulating film thereon, a wiring in the first insulating film, a first electrode film on the first insulating film, a stacked body on the first electrode film, made of alternating second insulating films and second electrode films, a first insulating member extending in a direction to penetrate the stacked body, a first semiconductor film around the first insulating member and connected to the first electrode film, a third insulating film around the first semiconductor film, a first conductive member extending in the direction to penetrate the stacked body and the first electrode film, and connected to the wiring, and a fourth insulating film around the first conductive member. The fourth insulating film has the same film structure as the third insulating film.

Semiconductor memory device including stacked body with conductivity and insulating members and method for manufacturing the same

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Yokkaichi, Japan

Hideo Wada