Nec Corporation

Nec Electronics Corporation

Saitama Medical University

Hideo Toyoshima

Tohru Miwa

Shigeru Kuhara

Tomotaka Yokoo

Yuji Ando

Koichi Takeda

Nobuhiro Yamada

Yasushi Okazaki

Izumi Sugahara

Provided are a new peptide, a vector inserting a DNA that codes said peptide, a transformant obtained by transformation with that vector, and applications of said peptide, vector and transformant. The peptide comprises an amino acid sequence set forth in SEQ ID NO: 1, or an amino acid sequence obtained by substituting, deleting or adding one or more amino acids to/from the amino acid sequence set forth in SEQ ID NO: 1. This peptide and the vector inserting a DNA that codes this peptide are suitable for use in an agent for promoting the proliferation of pancreatic hormone-producing cells, or a differentiation induction promoter that induces differentiation to pancreatic hormone-producing cells.

Peptide and application thereof

Disclosed are: an insulin secretion inducer; an insulin secretion-inducing composition; a process for the production of the composition; an accelerator for increasing the number of pancreatic &#x3b2;-cells; a composition for increasing the number of pancreatic &#x3b2;-cells; a process for the production of the composition; and a viral vector for gene therapy. The insulin secretion inducer or the accelerator for increasing the number of pancreatic &#x3b2;-cells comprises a polypeptide having an amino acid sequence encoded by DNA that is known to encode a membrane protein Tm4sf20 (transmembrane 4 L six family member 20) or the like or a fragment of the polypeptide as an active ingredient.

Method of treatment of diabestes or reduction in pancreatic beta-cells

In a shadow RAM using a ferroelectric capacitor, a memory cell constituted by connecting a ferroelectric capacitor directly to each of storage nodes of an unloaded four-transistor SRAM cell formed of four transistors. Thus, the number of transistors per one memory cell can be reduced by two transistors, so that a storage capacity can be increased further.

Shadow RAM cell using a ferroelectric capacitor

Shadow ram cell using a ferroelectric capacitor

For a memory cell comprising: a pair of memory nodes for holding a pair of complementary voltages; a pair of switching elements for controlling the connection between each memory node and a bit line corresponding to the memory node according to ON/OFF control by a common word line; and a pair of ferroelectric capacitors each of which is connected to a plate line and corresponding one of the memory nodes, storing operation of the memory cell is carried out by swinging the voltage of the plate line between a first voltage that is higher than power supply voltage of the memory cell and a second voltage that is lower than the ground potential while keeping the switching elements in off states, thereby remanent polarization of the ferroelectric capacitors is made larger. In addition, recall operation of the memory cell is carried out by driving the plate line to a third voltage that is higher than the power supply voltage or a fourth voltage that is lower than the ground potential so as to enlarge operation margin. By such storing operation and recall operation, the reliability of nonvolatile memory under a low power supply voltage can be improved.

Memory cell, nonvolatile memory device and control method therefor improving reliability under low power supply voltage

A semiconductor memory system is provided in which a wave-pipeline operational frequency is enhanced by reducing the cycle time through a reduction in a difference in the signal delay time caused by differences of data path lengths. A delay circuit is inserted into a signal path having a smaller delay time between an address input section and data output section, thereby reducing a difference in the signal delay time caused by differences of data path lengths, which in turn reduces the cycle time to enhance the wave-pipeline operational frequency. Alternatively, an arrangement may be made to increase the signal delay time of a driver and/or sense amplifier for a smaller signal path length. In another aspect, a maximum differences in voltage drops between memory cells is reduced by controlling the resistance of a charge section for a bit line.

High-speed semiconductor memory system

A semiconductor memory includes a plurality of first memory cell arrays, a pair of first common data lines which are provided for the plurality of first memory cell arrays, and a sensing section including a pair of first bipolar transistors whose emitters are respectively connected to the first common data lines and first constant current sources. Each first memory cell arrays includes a plurality of second memory cell arrays, a pair of second common data lines, a first differential amplifier including a second constant current source and a pair of second bipolar transistors whose bases are respectively connected to the second common data lines, whose bases are connected to the second constant current source together, and whose collectors are connected to the first common data lines, and a third constant current source of a second differential amplifier. Each second memory cell arrays includes a plurality of third memory cell arrays, a pair of third common data lines, a pair of third bipolar transistors whose bases are respectively connected to the third common data lines, whose emitters are connected to the third constant current source together to constitute the second differential amplifier, and whose collectors are respectively connected to the second common data lines, and a first control circuit for selectively activating the pair of third bipolar transistors. Each third memory cell arrays includes a pair of bit lines, a plurality of memory cells connected to the pair of bit lines, and a second control circuit for selectively connecting the pair of bit lines to the pair of second common data lines.

Semiconductor memory operable with low power supply voltage

There is disclosed a resonant-tunneling bipolar transistor with a quantum-well comprising an inversion forming layer of an n-type gallium arsenide which is in contact with a first potential barrier layer of an undoped aluminum gallium arsenide partially defining the quantum-well, so that a two-dimensional hole gas layer serving as a base region takes place at the interface between the inversion forming layer and the first potential barrier layer due to differences in electron affinity and in the sum of electron affinity and energy bandgap upon application of an appropriate biasing voltage, thereby producing hot electrons injected from an emitter region through the quantum-well into the base region by the agency of a resonant-tunneling phenomenon.

Growing community of inventors

Tokyo, Japan

Hideo Toyoshima