Hitachi, Ltd.

Hitachi Plant Engineering Construction Co., Ltd.

Hideo Sunami

Tokuo Kure

Yoshifumi Kawamoto

Masanobu Miyao

ShinIchiro Kimura

Kiyoo Itoh

Toru Kaga

Toshikazu Shimada

Kazuo Nakazato

Hiroshi Mizuta

Katsuhiro Shimohigashi

Yoshio Sakai

Makoto Ohkura

Toshiaki Masuhara

Osamu Minato

Yoshiaki Kamigaki

Terunori Warabisako

Masao Tamura

Mitsumasa Koyanagi

Toshiyuki Mine

Masahiro Moniwa

Shinji Shimizu

Ken Yamaguchi

Tatsuya Teshima

Yasuo Wada

Hiroo Masuda

Eiji Takeda

Kikuo Kusukawa

Yokichi Itoh

Katsutaka Kimura

Shoji Shukuri

Ryoichi Hori

Iwao Takemoto

Shinichiro Kimura

Masaharu Kubo

Eiichi Murakami

Michio Suzuki

Takahiko Kato

Toshikazu Nishino

Nobuyoshi Natsuaki

Atsushi Hiraiwa

Yoshimune Hagiwara

Yutaka Misawa

Norikazu Hashimoto

Fumiyuki Inose

Atsushi Saiki

Kiyoshi Miyake

Takashi Tokuyama

Shojiro Asai

Kiyoo Ito

Michiyoshi Maki

Shin-ichiro Kimura

Naotsugu Yoshihiro

Kinichiro Asami

A controllable conduction device in the form of a transistor comprises source and drain regionsbetween which extends a conduction path P for charge carriers, a gatefor controlling charge carrier flow along the conduction path and a multiple layer structureproviding a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Controllable conduction device with electrostatic barrier

Semiconductor memory device and manufacturing method

Semiconductor memory device and manufacturing method thereof

A semiconductor memory having a capacitor formed by utilizing a groove formed in a semiconductor substrate and an insulated gate field effect transistor and suppressing expansion of a depletion layer from the groove, and a method for fabricating the same are disclosed. An area occupied by each memory cell can be made very small and a distance between the memory cells can also be made very small, accordingly, high density integration is facilitated.

Method for fabricating semiconductor memory with a groove

A controllable conduction device in the form of a transistor comprises source and drain regions,between which extends a conduction path P for charge carriers, a gate,for controlling charge carrier flow along the conduction path and a multiple layer structure,providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Controllable conduction device

A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.

Semiconductor memory with trench capacitor

Technology for using a wiring of a superconductive material in semiconductor integrated circuit device. An isolation layer and/or a barrier layer are provided for preventing diffusion of harmful composition of the superconductive material for the semiconductor device. Control of a circuit can be made utilizing the characteristics of a superconductive material. Also, the characteristics of a superconductive material may be controlled. A method of forming a layer of superconductive material, well compatible with the widely used process of manufacturing integrated circuit devices, is also disclosed.

Semiconductor integrated circuit device having superconductive layer and

A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Semiconductor memory

A semiconductor memory comprises a switching device and a charge-storage device disposed at the upper and lower sides, respectively, of each of semiconductor islands. The islands are formed on a semiconductor substrate that is completely isolated from the semiconductor substrate by an insulator. The switching device and charge-storage device are substantially the same width. The memory cell structure is extremely small. The cell structure is highly resistant to alpha-particles and is formed self-aligned. During manufacture, the SiO.sub.2 island is oxidized adjacent its lower end to insulate the island from the substrate.

Process for manufacturing vertical dynamic random access memories

A semiconductor memory is provided having a capacitor formed by utilizing a groove formed in a semiconductor substrate and an insulated gate field effect transistor. In particular, an arrangement is provided to prevent a depletion region formed around the groove from growing into an adjacent capacitor. By virtue of this, both the area occupied by each memory cell and the distance between the memory cells can be made very small. Accordingly, high density integration is facilitated.

Semiconductor memory and method for fabricating the same

A megabit dynamic random access memory realizing high integration and high reliability is disclosed. The need for an allowance for photomask alignment which is carried out to produce a stacked capacitor memory cell is eliminated. The plate electrode of each memory cell is isolated from the corresponding data line in a memory array by means of an insulating film which is self-alignedly provided around the plate electrode.

Semiconductor memory having stacked capacitor

The side wall part of a recess dug in a Si substrate is used as the major part of the electrode surface of a capacitor, whereby the electrode area is enlarged without enlarging a plane area. Thus, a desired capacitor capacitance can be attained without increasing the breakdown of an insulator film ascribable to the conventional approach of thinning of the insulator film. In addition, a vertical switching transistor is formed on the Si substrate, whereby the Si substrate can be entirely utilized for the formation of the capacitor.

Semiconductor memory and method of producing the same

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Tokyo, Japan

Hideo Sunami