Kabushiki Kaisha Toshiba

International Business Machines Corporation

Hideo Sakai

Tomotaka Saito

Akihiro Yamazaki

Kiyoharu Oikawa

Kazumasa Ando

Kazuhiko Miki

Miki Sakai

A seat ticket auction method and system using the Internet is provided. A user submits a tender for the auction of each seat while referring to a seating table, and also performs a search of an exhibition before submitting a tender during the auction. Further, when the seating table is referred to, information for a seat appropriate for a person in a wheelchair, and a simulation (view) of what a user will see of the stage from a seat are displayed on the terminal of the user. Three tender types, a personal tender, a complete group tender and an incomplete group tender can be selected. For the complete group tender, when a bid is not successful for all the members of the group, the bid is abandoned.

Auction method, auction system, and program product therefor

Systems and methods for voice synthesis are disclosed for providing a synthesized voice message that is consonant with the taste of a customer and a program storage device readable by machine to perform method steps for voice synthesis. In accordance with an order from a customer received via a network, a service provider generates voice synthesis data, based on voice characteristic data for a speaker chosen by the customer, that is produced for a sentence input by the customer, and prepares to deliver the voice synthesis data to the customer. At this time, a transaction number is provided for the order received from the customer, and subsequently, when the transaction number is presented by the customer, the generated voice synthesis data are delivered to the customer. The customer then loads the received voice synthesis data into a device that reproduces the voiced sentence.

Systems and methods for voice synthesis

A nonvolatile semiconductor memory of this invention includes a data storage read cell in which the threshold is set to turn on/off the read cell in accordance with storage data upon selection, a reference cell in which the threshold is set to turn on the reference cell upon selection, and a flip-flop type amplifier for reading out whether the read cell is an ON or OFF cell. In this nonvolatile semiconductor memory, whether the read cell is an ON or OFF cell is read out by comparing changes in bit line voltages of the read and reference cells using the flip-flop type sense amplifier by a method of performing precharge and then discharge. At this time, a word line connected to the read cell is set to a selected state in synchronism with the start of precharge, and a word line connected to the reference cell is set to a selected state in synchronism with the end of precharge.

Nonvolatile semiconductor memory with read circuit using flip-flop type

The present invention provides a logic circuit comprising a first power terminal, a second power terminal set at a higher potential than the first power terminal, a first FET of a first conductivity having a current path coupled to the first power terminal, a second FET of a second conductivity having a current path coupled to the second power terminal, and an input terminal commonly coupled to gate terminals of the first and second FETs, the first FET and the second FET having a relationship expressed approximately by the following equation: ##EQU1## where R.sub.S is a resistance of a resistor element parasitically produced between the first power terminal and the current path of the first FET. R.sub.D is a resistance of a resistor element parasitically produced between the second power terminal and the current path of the second FET, W.sub.N is a channel width of the first FET, W.sub.P is a channel width of the second FET, L.sub.N is a channel length of the first FET, L.sub.P is a channel length of the second FET, .mu..sub.N is a first carrier mobililty of the first FET, and .mu..sub.P is a second carrier mobility of the second FET.

Chopper type comparator

An inverter circuit according to this invention includes n- and p-type field effect transistors having predetermined wiring resistances and gates and drains connected with each other, a first power source connected to the source of the n-type field effect transistor, a power source connected to the source of the p-type field effect transistor, and first and second negative feedback switching transistors connected in parallel between the gates and the drains of the n- and p-type field effect transistors. Assuming that the channel length and width of the first insulating gate field effect transistor are L.sub.N and W.sub.N, respectively, and the wiring resistance thereof is R.sub.S, that the channel length and width of the second insulating gate field effect transistor are L.sub.P and W.sub.P, respectively, and the wiring resistance thereof is R.sub.D, and that carrier mobilities of the first and second insulating gate field effect transistors are .mu..sub.N and .mu..sub.P, respectively, a relation represented by: ##EQU1## is approximately satisfied. A voltage corresponding to a difference between a reference voltage and a comparison input is input from the connected gates, and data is output from the connected drains.

Inverter circuit and chopper type comparator circuit using the same

A transfer gate is made up of at least two p-channel MOS FETs and at least two n-channel MOS FETs. The current paths of the n-channel MOS FETs are connected in series, and the conduction of the FETs is controlled by a first control signal applied to the gates thereof. The current paths of the p-channel MOS FETs are also connected in series, and the conduction of the FETs is controlled by a second control signal applied to the gates thereof. The first and second control signals are opposite phase. The series circuit of the current paths of the p-channel FETs is connected in parallel to the series circuit of the current paths of the n-channel FETs. The p-channel FETs are formed in at least two n-type well regions, which is formed in the major surface region of a p-type semiconductor substrate at different locations separated from each other by predetermined distances.

Transfer gate with the improved cut-off characteristic

One of analog input voltages applied to a plurality of analog input terminals is selected by means of analog switches connected to the respective analog input terminals and supplied to a common terminal. In this case, each of the analog switches permits selective supply of the potential of a corresponding one of the plurality of analog input terminals in response to a control signal supplied from a controller. The common terminal is connected to the positive input terminal of a comparator. The comparator compares the voltage with a digital output value from the controller which is converted into an analog voltage by means of a D/A converter. Further, the controller generates a preset control signal in an inhibition period during which supply of a voltage from the plurality of analog input terminals to the common terminal is inhibited. An initial potential setting circuit sets the potential of the common terminal to a voltage level equal to substantially one-half the maximum voltage level of the analog input voltages applied to the plurality of analog input terminals.

Growing community of inventors

Yokohama, Japan

Hideo Sakai