Hitachi, Ltd.

Hideo Ota

Fuminobu Komura

Koichi Homma

Masao Takatoo

Youichi Seto

Yutaka Kubo

Morio Kanasaki

Tadaaki Mishima

In a method of recognizing a pattern of a gray level image the image to be processed is subjected to a normalization process, local gray level feature parameters are extracted from the normalized image at its sampling points, and the pattern is identified by using the extracted feature parameters in accordance with a predetermined recognition procedure. An apparatus for recognizing a pattern of a gray level includes a memory for storing a gray level image having several brightness tone levels, a normalization circuit for normalizing the brightness of the gray level image to be processed, an extraction circuit for extracting local gray level feature parameters from the obtained normality image at specific points, and a recognition circuit for identifying the pattern by using the feature parameters in accordance with a predetermined.

Method and apparatus for recognizing pattern of gray level image

Distortion models consisting of two forward and backward reciprocating planes that let a corrected image correspond to an uncorrected image for each scanning direction are constituted to let an uncorrected satellite image scanned by a reciprocating scanning sensor with scanning overlap or scanning underlap correspond to a corrected image after distortion correction, by means of a continuous mapping function on a 1:1 basis. It is determined whether each point on the corrected image is a point on an overlapping scan or on an underlapping scan or on a normal scan from the existence of a real point on the distortion models.

Image correction processing method

A data input/output system is provided for transfer of data between a large capacity data source and a large-capacity memory. The data input/output control information is supplied from a processor. If the actual time between input/output information units from the large-capacity data source is shorter than that time determined by a program in the processor, an interruption signal is generated to be in time for the input/output timing of the next input/output data unit. The system permits continuous data transfer switching from one input/output data unit to the next input/output data unit without use of the program in the processor.

Dynamically buffered data transfer system for large capacity data source

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Hitachi, Japan

Hideo Ota