Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Hideo Nishimatsu

Takeshi Mori

Akira Iwamoto

Hitoshi Nakatani

Hiroaki Nishimura

Toshiro Nishimura

Yuichiro Tachibana

Katsuya Kitano

Toru Wanibuchi

Yuji Takenaka

Akihiro Matsumoto

An information processing apparatusincludes: a first casinghaving an operation sectionprovided on a top surface; a second casinghaving a display provided thereon; an opening and closing mechanismconfigured to connect a far side portion of the first casingto the second casingsuch that the information processing apparatusis openable and closable; and a beltprovided on a back surface side of the first casing. The beltextends diagonally on a back surfaceof the first casingfrom a mounting portion provided on one side surfaceside of the first casing, so as to approach the far side portion of the first casingas a distance from the one side surfaceside is increased, and reaches a mounting portion provided on a far side of the first casing

Information processing apparatus

An electronic device comprises a main battery used as a drive power source for driving the electronic device, a secondary battery used as a drive power source instead of the main battery when the main battery cannot be used, a battery detection unit that detects an event of removal of the main battery from the electronic device, and a power control unit that changes the drive power source from the main battery to the secondary battery and controls operation of the electronic device to reduce power consumption by the electronic device when removal of the main battery is detected by the battery detection unit.

Electronic device

A memory includes a memory cell array unit, a plurality of memory cell bit lines connected to the memory cell array unit, a plurality of column selecting gates, and a plurality of sub data lines connected to the memory cell bit lines via the column selecting gates. A column selector serves to select and make conductive members of the column selecting gates so that data can be transmitted between successive members of the memory cell bit lines and the sub data lines. The memory further includes N-bit main data lines, where N denotes a given natural number. In addition, the memory includes data line selecting gates. The sub data lines are connected to the main data lines via the data line selecting gates. A data line selector serves to select and make conductive members of the data line selecting gates so that data can be transmitted between N successive members of the sub data lines and the main data lines.

Semiconductor memory having multiple data I/O with bit aligned access

Growing community of inventors

Osaka, Japan

Hideo Nishimatsu