Fujitsu Corporation

Hideo Monma

Takeshi Sasaki

Masayuki Takahashi

Masato Ishiguro

Tetsuo Kawano

Shunzo Ohta

Yoshinori Enomoto

A semiconductor device comprises a test signal generating circuit for generating a test signal having an arbitrary frequency, a first buffer for selectively outputting one of the test signal and an external input signal, at least one test circuit supplied with an output signal of the first buffer, an external output terminal, a logic circuit, a second buffer for selectively supplying to the external terminal one of the test signal from the test circuit and an output signal of the logic circuit, and a switching signal generating circuit for generating switching signals for the first and second buffers. The state of the test circuit is checked by use of the test signal to indirectly determine the state of the logic circuit.

Semiconductor device having a test circuit

A circuit for checking the integrity of interconnections between chips in a chip-on-chip type IC device is fabricated in respective portions on the lower and upper chips in peripheral areas thereof intermediate the inner logic circuit of each chip and the corresponding bonding pads. Selection circuits connected between the inner logic circuit signal terminals and the corresponding bonding pads of the chip are switched by control signals to be isolated and permit normal operation of the chip or to a checking mode to isolate the inner logic circuit and permit transmission of test signals through the interconnections. The test signals received through the interconnections are compared with the test signals as transmitted to determine the integrity of the individual interconnections. The disclosed apparatus and method provide for testing of the integrity of interconnections defining single direction signal paths of individual interconnections, as between the upper and lower chips, and for selectively bidirectional transmission through the individual interconnections.

Chip on chip type integrated circuit device

A gate array is disclosed having a plurality of basic cells each comprising a transistor whose gm is as low as one fifth to one twentieth that of the transistors in a conventional gate array. The low gm is provided by reducing the W/L ratio of the gate region of the transistor. The basic cell having the transistor of the low gm is formed to replace the conventional basic cell at a specified position in a specified basic cell array. The transistor of low gm reduces the number of basic cells necessary for forming a delay circuit, and elminates the need for an external resistance component which was formerly required when a pull-up or pull-down circuit or a monostable multivibrator was formed in the gate array.

Gate array

Integrated circuit with frequency-dividing circuits capable of being

A quick feeding system for feeding quick counting pulses to a counter, such as an hours counter of an electronic clock of the digital display type, comprising frequency dividing circuits, a switch for effecting a quick feed of pulses to the counter and a quick feed pulse generation circuit connected between one of the frequency dividing circuits and the counter.

Growing community of inventors

Kawasaki, Japan

Hideo Monma