Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Renesas Technology Corp.

Other

Hideo Maejima

Masahiro Iwamura

Koyo Katsura

Takashi Hotta

Shigeya Tanaka

Tadaaki Bandoh

Ikuro Masuda

Yasuhiro Nakatsuka

Kozaburo Kurita

Hisashi Kajiwara

Kazuo Kato

Sin-ichi Sinoda

Tetsuo Nakano

Hiroshi Takeda

Hiroyuki Kida

Ikuya Kawasaki

Junichi Nishimoto

Keiichi Kurakazu

Masahiro Ueno

Noboru Masuda

Yoshiki Kobayashi

Hidekazu Matsumoto

Kouzaburou Kurita

Hiromichi Yamada

Atsuo Watanabe

Yasushi Akao

Hiroyuki Itoh

Kazutaka Mori

Takashi Akioka

Takahiro Nagano

Tadahiko Nishimukai

Kinya Mitsumoto

Toshimasa Kihara

Seigou Yukutake

Shigeo Kuboki

Hiroaki Nakanishi

Kazunori Nakajima

Kazumi Hatayama

Terumine Hayashi

Shirou Baba

Atsuo Hotta

Tooru Komagawa

Shyoichi Miyazawa

Hajime Yasuda

Hisao Sasaki

Kunihiko Ohnuma

The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machine cycle at a time are processed in parallel by the plurality of arithmetic operation units.

Data processor

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal Kwhich is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal Kand the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.

Information processor and information processing system utilizing interface for synchronizing clock signal

For the tradeoffs between a lower consumption power of a microprocessor and its process speed, a plurality of clocks and power supply voltages are supplied to each of functional units to and a clock switching circuit and a power switching circuit are provided in each of the functional units. When a program mainly using a particular functional unit, e.g., FPU is executed, the operation speed of FPU is raised more than that in a normal operation mode. To this end, a consumption power control circuit supplies a power/clock switching signal to FPU This power/clock switching signal instructs to raise the clock frequency and power supply voltage to be used by FPU In order to compensate for an increase in the consumption power to be caused by the high speed operation of FPU the consumption power control circuit also supplies a power/clock signal to another functional unit, e.g., CPU This power/clock switching signal instructs to lower the clock frequency of CPU

Microprocessor

A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second processor executes an instruction of the second instructions set. The first processor may be a reduced instruction set computer (RISC) type processor, the second processor may be a very long instruction word (VLIW) type processor, the first instruction set may be a RISC instruction set and the second instruction set may be a VLIW instruction set. The predetermined instruction of the RISC instruction set executed by the first processor may be a branch instruction causing a branch to a specific address space at which VLIW instructions are stored. Thereafter, the VLIW instructions at the specific address space are executed by the VLIW type processor.

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K , And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K .

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.

Low power consumption semiconductor integrated circuit device and microprocessor

In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunction display. When image data are to be inputted or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings. The resultant effect is that it is unnecessary to increase the number of refresh memories corresponding to the displayed frame and that the external parts can be simplified to contribute to the improvement in the reliability.

Display controller

A data processing apparatus which processes data held in memory. The data processing apparatus includes an address operation unit which obtains an address to read one-word data from the memory, wherein the one-word data is a unit of data access to the memory, and a logical operation unit which determines a content of an operation on a field basis based on information which designates the number of bits per field to construct one-word data with a plurality of fields having a same number of bits. The logical operation unit, based on the content thus determined, performs the operation in parallel on the fields of the one-word data read from the memory by the address thus obtained.

Graphic pattern processing apparatus

Data processor for the parallel processing of a plurality of instructions

In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunctional display. When image data are to be inputted or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings. The resultant effect is that it is unnecessary to increase the number of refresh memories corresponding to the displayed frame and that the external parts can be simplified to contribute to the improvement in the reliability.

Low power consumption semiconductor integrated circuit device and

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

Information processor and information processing system utilizing clock

A semiconductor device and a computer system, incorporating the same, is capable of capturing an external signal at a high speed and stably operating independent of the duty ratio of a clock signal. An external signal ADD is captured into an address latch 22 by a level latch. The level latch is controlled to a through state at the timing in which the external signal is decided and controlled to a latched state in the decision period of the external signal. A pulse generation circuit controls the timing for switching a latch to the through state to a desired timing by a pulse generation circuit 30 in a chip. According to the above structure, the capture of the external signal ADD can be accelerated because the capture of the signal is determined by the setup timing. Moreover, because a latching period is controlled by the pulse generation circuit in the chip, operations are performed in a stable manner without having to depend upon the pulse width of an external clock CLK.

Semiconductor device capable of holding signals independent of the pulse

Growing community of inventors

Hitachi, Japan

Hideo Maejima