Nec Corporation

Nissan Motor Company Limited

Fuji Kiko Co., Ltd.

Fujigiken Kogyo Co., Ltd.

Hideo Ishida

Nobuyuki Mizukoshi

Yasushi Ooi

Noboru Sato

Takeo Tamura

Kiyoshi Kirino

Kimio Izawa

In an ATM cell transmission system having an ATM layer device (,), a data path interface (,) and a plurality of normal PHY (Physical) layer devices (,-,to,-M) according to Utopia Level 2 specification, the ATM layer device (,) comprises: a cell buffer (,); FIFO memories (,-,to,-M) each corresponding to each of the normal PHY layer devices (,-,to,-M); an output controller (,&prime;) for controlling the cell buffer (,) to output an ATM cell to be transmitted through one of the normal PHY layer devices (,-,to,-M) into corresponding one of the FIFO memories (,-,to,-M) on condition that the ATM cell is stored in the cell buffer (,) and the corresponding one of the FIFO memories (,-,to,-M) is not full; and a cell transmission controller (,) for performing polling of the normal PHY layer devices (,-,to,-M), designating a selected PHY layer device among the normal PHY layer devices (,-,to,-M) which have returned the HIGH level of the cell transmission allowance signal (TxClav) to the polling and whereof corresponding FIFO memories (,-,to,-M) are not empty, selecting one of the FIFO memories (,-,to,-M) corresponding to the selected PHY layer device as a next sender of cell data to be transmitted through the data path interface (,), and designating the selected PHY layer device at an end of the current transmission cycle as a next receiver of the cell data.

ATM cell transmission system

In an ATM device comprising a switch core,a port shaping unit,is arranged within the switch core,to carry out a port shaping operation. The port shaping unit,controls reading timing of each cell stored in a shared buffer,Therefore, a delay to absorb the CDV is decided by the reading timing and the port shaping operation is achieved within the ATM device without attaching any additional memories to the ATM device.

ATM device and shaping method

A V-belt is mounted on a first fixed conical plate and second fixed conical plate of a lower unit, and an upper unit is made to descend. A first movable conical plate and second movable conical plate are installed in the upper unit, and the V-belt is gripped between the fixed conical plates and movable conical plates. When a rotary actuator of the lower unit draws a drawbar which extends below the movable conical plate downwards, a predetermined pressure is applied to the V-belt. The first movable conical plate and first fixed conical plate are rotated in this state to drive the V-belt, and a noise test is performed.

V-belt noise tester and testing method

Slackness of a ball spline joint which engages a first member of a circular shape and a second member fitted outside of the first member is measured by measuring a displacement of a first measurement point (P1) and a second measurement point (P2). The measurement points are set on the radial line passing through the center of the first member and the center of the spline groove. Using the distances (R1, R2) between the center of the first member and the measurement points (P1, P2), and the displacement amount (A1, A2) of the measurement points (P1, P2) under a predetermined relative torque, the slackness of the joint is calculated. By arranging the measurement points (P1, P2) on either side of the center of the first member, the effect of measurement error in the displacement amount (A1, A2) on the calculation is reduced.

Ball spline joint slackness measuring method and measuring apparatus

An image processing apparatus includes a color difference data interpolator for alternately calculating the interpolation data items of color difference signals Cb and Cr in a time-sharing process. The interpolator includes registers for storing therein data items sb and sr of input color difference data items ICb and ICr, selectors for selecting either one of the data items ICb, sb, ICr, and sr and respectively outputting data items t1 and t2, an internal ratio calculating section for receiving the data items t1 and t2 to conduct an operation of (3.times.t1+t2) and outputting internal ratio data D, and registers for storing color difference Cb data B supplied from the data D. Consequently, an image processing circuit for the interpolation to enlarge the picture size of video data in the compressed YCbCr data format is reduced in the hardware size.

Image processing apparatus

An image processing system and method capable of reducing hardware scale to improve processing speed. The G conversion section includes a third product producer for producing a third product from a first intermediate product corresponding to a first common partial bit string of multipliers of a color difference Cr for R and G conversions, and a fourth product producer for producing a fourth product from a second intermediate product corresponding to a second common partial bit string of multipliers of a color difference Cb for B and G conversions, and intermediate calculation data of a fixed factor multiplication of the color difference Cr for the R data conversion and intermediate calculation data of a fixed factor multiplication of the color difference Cb for the B data conversion are utilized for the conversion calculation of the data G.

Image processing system and method for converting YCbCr data composed of

An address generating circuit having a two-dimensional coding table which has respective coded words corresponding to a combination of x and y where the value of event A is determined as x and the value of event B as y (x and y are positive integers) between two events A and B, and stores the coded words in an address corresponding to each combination of x and y; coincidence detectors which input the values x and y of the events A and B and detect whether these values coincide with the integer of 1 to S (S is the maximum number among the integers satisfying S+log.sub.2 S&lt;P and P is a positive integer); comparators which examine whether the inputted y satisfies x+log.sub.2 y.ltoreq.P for each integral number of x, and examine whether the inputted x satisfies y+log.sub.2 x.ltoreq.P for each integral number of y; an escape signal generation section which outputs an escape signal according to the output of the coincidence detectors and the comparators; an address generation section which generates and outputs an address signal from values x and y and an identification address for identifying that x and y are integers; a priority control section which inputs the output from the coincidence detectors, determines which signal is outputted with precedence and outputs it; and a multiplexer which selects and outputs an address signal in accordance with the output from the priority control section.

Address generating circuit of a two-dimensional coding table

Disclosed herein is a limiter circuit for limiting an output data to a limit value when an input data exceeds in value the limit value. The limiter circuit includes an encoder responding to the input data and producing a first data indicative of an effective digit number of the value of the input data, a comparator comparing the first data with a second data indicative of an effective digit number of the limit value, and a decoder responding to the second data and producing a third data indicative of the limit value. One of the input data and the third data is selected and outputted as the output data through a selector responding to a comparison output of the comparator.

Limiter circuit producing data by use of comparison in effective digit

In an address formation circuit for an image processing, an address formation is separately processed in parallel like a pipeline by first and second address calculation means. The first address calculation means controllable by a program calculates a head address of a macroblock, and the second address calculation means calculates addresses of pixels within the macroblock on the basis of the head address calculated by the first address calculation means. An instruction memory stores the program and a data memory and a data file memory store address moving amounts required the calculations. A sequence controller controls an exclusive hardware. Hence, a high speed memory access like a real time image processing in the address formation can be possible and, when a complicated address pattern is required, an overhead of the address formation time in the instruction processing can be prevented.

Address formation circuit and method for continuously performing an

A seat back tilts forward when an actuating lever is pulled, and remains forward after the lever is released. The seat back is restored to a desired operating position by pushing it backward until it stops moving. The desired position is set by pulling a release lever, pushing the seat back to the desired position, and releasing the release lever.

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Tokyo, Japan

Hideo Ishida