Sanyo Electric Co., Ltd.

Hideo Imaizumi

Tsutomu Ishikawa

Kenichi Nakajima

Yoshiaki Takahashi

Takuji Kato

Akira Kabashima

An electronic equipment manufacturer has been bearing the burden to adjust variations in characteristics of semiconductor integrated circuits according to a conventional art. The device and the method of this invention include a microcomputer, signal processing circuit which processes an input signal accordingly to a control signal from the microcomputer and provides an output signal and a memory which stores adjustment values to adjust changes in signal characteristics due to variations in manufacturing of elements composing the signal processing unit. The microcomputer adjusts the changes in the signal characteristics of the signal processing circuit according to the adjustment values stored in the memory.

Semiconductor integrated circuit and adjustment method thereof

A frequency of a first VCO (12) for generating a carrier of a video IF signal is set by using a frequency of a second VCO (15) as reference. The oscillation frequency of the second VCO (15) is controlled in response to the phase difference between an output signal of the first VCO (12) and the video IF signal. As a result, the output signal phase of the first VCO (12) is adjusted, and the output signal is locked to a carrier frequency of the video IF signal. Thus, the oscillation frequency of the first VCO (12) can be set automatically. Further, a signal for the phase difference between the output signal of the first VCO (12) and the video IF signal is also applied to the first VCO (12), thereby improving the stability of circuit operation.

Double phase locked loop circuit

A television receiver includes a correction filter (10) having an inclination characteristic opposite to a slope of a video intermediate frequency signal. The video intermediate frequency signal correction by the correction filter is applied to a PLL circuit (11) and the PLL circuit generates a carrier signal of a video intermediate frequency locked to the video intermediate frequency signal. A synchronous detecting circuit (16) detects the video intermediate frequency signal before the correction in response to the signal output from the PLL circuit and outputs a video signal. At the same time, it generates a sound FM signal corresponding to a beat of the carrier signal of the video intermediate frequency and a carrier signal of a sound intermediate frequency. A sound detecting circuit (20) detects the sound FM signal and outputs a sound signal.

Detecting circuit which reduces buzz in a sound signal

A multi-channel sound signal received and detected in a TV receiver includes a main channel signal comprising a stereo sum (L+R) signal, a stereo pilot signal having a frequency of f.sub.H equal to the frequency of a horizontal synchronizing signal, and a sub-channel signal obtained by DSB modulation of a sub-carrier having a frequency of 2f.sub.H by a stereo difference (L-R) signal. In a TV multi-channel sound signal demodulator circuit, the sub-carrier is reproduced by a PLL circuit in response to the stereo pilot signal, to demodulate the stereo difference (L-R) signal using the sub-carrier. The stereo difference signal thus demodulated includes a 60Hz noise component due to interference between a sound signal and a video signal. However, the noise component is removed by a high-pass filter provided between a sub-channel signal demodulator circuit and a matrix circuit. Thus, right and left stereo signals R and L outputted from the matrix circuit do not include a noise component.

Growing community of inventors

Gunma, Japan

Hideo Imaizumi