Hitachi, Ltd.

Hideo Homma

Naohiro Momma

Yutaka Misawa

Masaya Adachi

Yutaka Kobayashi

Sukekazu Aratani

Ryuichi Saito

Atsuo Watanabe

Osamu Saito

Katsusuke Shimazaki

Takashi Akioka

Hidekatsu Onose

Hirokazu Inoue

Toshinari Shibasaki

Sadao Okano

An illuminating device includes a light-condensing sheet, a light-emitting portion, and a control unit. The light-condensing sheet includes a plurality of lenses each with a light-condensing function ranged on a light transmittance substrate. The light-emitting portion is opposed to the light-condensing sheet and includes light-emitting areas with respective dimensions. The control unit switches a luminous state of the light-emitting area to a non-luminous state or vice versa. A display device is provided with the illuminating device described above.

Illuminating device and display device

A semiconductor device includes a trench formed on a source side of a drift region, a p-type gate region and a gate formed at the bottom of the trench, and the source formed over the entire surface of the unit device through an insulating film. The narrowest portion of a channel of the device is deeper than one-half the junction depth of the p-type gate region. This allows the width of the channel on the drain side to be reduced even when a lower energy ion implantation manufacturing process is used.

Semiconductor device

A semiconductor integrated circuit device capable of having a high integration density and excellent performance and a method of fabricating the semiconductor integrated circuit device are disclosed. In this semiconductor integrated circuit device, a connecting conductor for connecting gate wiring which is formed on a field oxide film and extended from the gate of a MOSFET, to the source/drain region of another MOSFET is interposed between the gate wiring and one of two side space layers for defining the width of the gate wiring.

Semiconductor integrated circuit device with multiplayered wiring

A semiconductor device has a structure in which two semiconductor substrates are coupled to each other through a semiconductor oxide film and a metal silicide film, and a semiconductor element, for example, a bi-polar transistor is formed in the semiconductor substrate on the metal silicide film side, whereby a metal silicide layer having a high melting point is provided beneath one region of the bi-polar transistor for example, an n.sup.+ buried collector layer and in ohmic contact with the n.sup.+ buried collector layer. An electrical isolation between the adjacent semiconductor elements is made by an insulating layer.

A method of fabricating a semiconductor device includes the steps of: forming at least one first semiconductor region of a first conductivity type and at least one second semiconductor region of a second conductivity type in a main surface of a semiconductor layer of the first conductivity type; forming a three-layer film having a desired shape on each of the first and second semiconductor regions, the three-layer film being made up of a bottom layer which is a conductive film, an intermediate layer which is a silicon nitride film, and a top layer which is a polycrystalline silicon film doped with one of arsenic and phosphorus; forming a first insulating layer on the side wall of the three-layer film; forming a second polycrystalline silicon film on the whole surface, and diffusing one of arsenic and phosphorus from the first polycrystalline silicon film into the second polycrystalline silicon film; selectively etching off the first polycrystalline silicon film and that portion of the second polycrystalline silicon film, in which one of arsenic and phosphorus has been diffused; forming a second insulating layer at least on the surface of the portion of the second polycrystalline silicon film which exists on the second semiconductor region; removing the silicon nitride film and the conductive film which exist on the second semiconductor region, while using the second insulating layer as a mask, to form an aperture; and forming a third polycrystalline silicone film so that the aperture is covered by the third polycrystalline silicon film.

Method of fabricating bipolar transistors and insulated gate field

A dual-enclosure semi-closed diffusion wherein an outer enclosure is evacuatable and an inner enclosure has a limited aperture, the inner enclosure includes a diffusion vessel having an aperture and a baffle for partially blocking the aperture to leave the limited aperture. The outer enclosure is not directly exposed to impurity vapor and sustains a pressure difference, while the inner enclosure is not subjected to a substantial pressure difference.

Diffusion of impurities into semiconductor using semi-closed inner

A method of manufacturing a semiconductor device comprising preparing a semiconductor substrate which includes at least three semiconductor layers of alternately different conductivity types and in which one of the semiconductor layers is divided into a plurality of respectively independent regions on each of which an electrode film is provided. When one of the regions of the semiconductor layer is found defective, a substantial portion of the electrode film provided on the defective region is removed by trimming to lower the surface level of the electrode film relative to the others.

Growing community of inventors

Hitachi, Japan

Hideo Homma