Hitachi, Ltd.

Sony Corporation

Sapporo Breweries Limited

Hideo Harada

Masahiro Shiraishi

Satoshi Nishikawa

Tadanobu Toba

Takumi Uezono

Yusuke Kanno

Kaoru Umeda

Toru Motoya

Keisuke Yamamoto

Hajime Kanda

Tetsuya Nakajima

Susumu Morita

Yoshinori Nishimura

Tomokazu Takaoka

Satoru Akasaka

Nobuchika Ishibashi

Katsunobu Natori

Ryuma Ikutani

Provided are a method of producing a beverage and a method of improving a flavor of a beverage by each of which the imparting of an undesirable aroma is suppressed. The method of producing a beverage according to one embodiment of the present invention is a method of producing a beverage using a raw material liquid, including adding hops that have been subjected to acid treatment to the raw material liquid. The method of improving a flavor of a beverage according to one embodiment of the present invention is a method of improving a flavor of a beverage to be produced using a raw material liquid, including adding hops that have been subjected to acid treatment to the raw material liquid, to thereby improve the flavor of the beverage.

Method for producing beverage and method for improving flavor of beverage

A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.

Application logic, and verification method and configuration method thereof

Provided is a semiconductor LSI design device that includes: a unit that generates a combinational circuit constituted by combining function blocks defined by a function block library from an application specification, by assigning connection information on an operation order of the function blocks; a unit that converts the combinational circuit to operation order information that is applicable to a sequential circuit in which a function block is used a plurality of times in a time-division manner; a unit that inversely converts the generated operation order information to a combinational circuit; a unit that verifies logical equivalence of the combinational circuit and the inversely converted combinational circuit; and a unit that combines the operation order information, the sequential circuit and a function block.

Semiconductor LSI design device and design method

The present invention includes a drawing data generating unit, a variation pattern that varies at regular intervals to be displayed, a display unit that displays drawing data, and a comparator that compares whether input signals are coincident, and the drawing data generating unit includes a receiver that receives data from a higher-level device, a drawing control unit that converts the data received from the higher-level device to drawing data, and a drawing memory that stores the drawing data. The drawing data generating unit and the variation pattern are redundantly configured, and the variation pattern is input to the drawing data generating unit. One output signal of the drawing data generating unit regarding drawing data including the variation pattern is transmitted to the display unit, a plurality of output signals from the drawing data generating unit are input to the comparator, and the comparator outputs a comparison result as a detection signal outside. This improves safety and reliability when severe safety criteria are required such as in a case of monitor-display in industrial plant equipment.

Display device

Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.

A control system includes an arithmetic device configured of an A system arithmetic unit including a data dividing unit, a B system arithmetic unit including a data dividing unit, and an A system communication control unit including a data combining unit and a collation unit, wherein the A system arithmetic unit and the B system arithmetic unit have a duplex configuration, the A system arithmetic unit and the B system arithmetic unit are separated by a gap, a frame output from the A system arithmetic unit is transmitted to a B system communication control unit through the A system communication control unit and an interface element, and a frame output from the B system arithmetic unit is transmitted to the A system communication control unit through the B system communication control unit and an interface element.

Control system

Tuning indicator apparatus is provided for use with a frequency synthesizer tuner of the type having a phase-locked loop including a reference oscillator, a variable frequency oscillator to produce a local oscillating signal, a programmable frequency divider coupled to the variable frequency oscillator for dividing the frequency of the local oscillating signal by a variable dividing ratio to produce a frequency-divided oscillating signal, a phase comparator for comparing the frequency-divided oscillating signal to the output of the reference oscillator to produce an error signal, and a feedback circuit for feeding back the error signal from the phase comparator to the variable frequency oscillator to adjust the frequency of the local oscillating signal and thereby establish a tuning condition of the tuner. The tuning indicator apparatus includes a counter for counting counter pulses supplied thereto, the count of this counter determining the dividing ratio of the programmable frequency divider. An indicating circuit is responsive to a change in at least a predetermined value of the count of this counter to indicate that the count has changed and, thus, that the tuning condition of the tuner has changed. In a preferred embodiment, a sound generator is provided to generate an audible indication of a change in the tuning condition.

Tuning indicator apparatus for a frequency synthesizer tuner

Tuning control apparatus is provided for use with a frequency synthesizer tuner of the type having a phase-locked loop including a reference oscillator, a variable frequency oscillator to produce a local oscillating signal, a programmable frequency divider coupled to the variable frequency oscillator for dividing the frequency of the local oscillating signal by a variable dividing ratio to produce a frequency-divided oscillating signal, a phase comparator for comparing the frequency-divided oscillating signal to the output of the reference oscillator to produce an error signal, and a feedback circuit for feeding back the error signal from the phase comparator to the variable frequency oscillator to adjust the frequency of the local oscillating signal and thereby establish a tuning condition of the tuner. The tuning control apparatus includes a counter for counting control pulses supplied thereto, the count of this counter determining the dividing ratio of the programmable frequency divider. A control pulse generator supplies control pulses to the counter. An adjusting circuit is operable to adjust the rate at which the control pulses are supplied to the counter for adjusting the speed at which the count of the counter and the dividing ratio of the programmable frequency divider changes. In one embodiment of this invention, a switching circuit is provided to be selectively operable to supply only a predetermined number of the control pulses to the counter so as to change the count of the latter, and thus the dividing ratio of the programmable frequency divider, by a predetermined step. Thus, the tuning condition of the frequency synthesizer tuner can be changed at a variable rate or, alternatively, in a stepwise manner.

Growing community of inventors

Tokyo, Japan

Hideo Harada