Mita Industrial Co., Ltd.

Megachips Corporation

Hideo Azumai

Satoshi Iwatsubo

Ariyoshi Hikosaka

Tetsuji Kajitani

Hiroyuki Fujita

Takuji Okumura

Toshikazu Yoshimizu

Tsukasa Matsushita

Hidemitsu Hirano

Takashi Kohno

Ikuhiro Omi

According to the image processing apparatus of the present invention, image data are entered with an input resolution of 16 dots/mm, yet allowing the use of a conventional image processing system with a resolution of 8 dots/mm, and there can be produced an image better in quality than a conventional one. First, pixel data with an input resolution of 16 dots/mm are subjected to resolution conversion using a resolution converting unit 21. The resolution conversion is made by an odd-numbered pixel thinning processing when the apparatus mode is set to a binary mode, and by a two pixel averaging processing when the apparatus mode is set to a half-tone mode. Then, pixel data of which resolution has been converted into 8 dots/mm, are supplied to an image processing unit 22, where an image processing is then executed on the pixel data.

Image forming apparatus capable of converting the resolution

A data managing device according to the present invention processes the same object pixel before and after variable magnification processing, and collectively manages processing data before and after the variable magnification processing by making access to a memory once. In the variable magnification processing before and after which the number of object pixels differs, 1-bit BF data for area separation processing performed before the variable magnification processing and 7-bit produced error data for error diffusion processing performed after the variable magnification processing are mixed, and data composed of a total of 8 bits which is obtained by the mixing is read out/written from and to the same address in a SRAM 4 at the same access timing. Therefore, at the time of reduction processing, a reduction processing control signal SMWAIT is produced, and error diffusion processing is stopped when the signal is at a high level.

Data managing device in image variable magnification processing apparatus

In accordance with the present invention, a quadratic differential values is first calculated, based on differences in the density data between an object pixel and respective peripheral pixels around the object pixel. The square value SS of the quadratic differential value S and the sum .SIGMA.SS obtained by adding up the square values SS of quadratic differential values for continuous five pixels are employed as determination values (step n1). The square sum .SIGMA.SS is compared with respective threshold values a, b and d, and the square value SS is compared with respective threshold values c, e and f (steps n2 to n6 and n8). Based on these comparison results, it is judged which image area among a character image area, gray-scale image area and dotted image area the object pixel belongs to. As for the image area judgement concerning the dotted image area, the final judgement that the object pixel belongs to the dotted image area is made only when nine continuous pixels including the object pixel are all judged to belong to the dotted image area. Since the square values SS and square sum .SIGMA.SS take only a positive value, the threshold values are set only in a positive range, and hence the image processing can be simplified. Further, by employing the square sum .SIGMA.SS, the states of the peripheral pixels can be taken into consideration for the image area judgement.

Image processing method and apparatus

An image data processing apparatus for performing processing using data corresponding to a plurality of lines which correspond to a plurality of scanning lines at the time of reading an image. For example, when processing is performed using data corresponding to three lines, that is, the present line, a line one ahead of the present line and a line two lines ahead of the present line, a line memory having a capacity of two lines is used. When the data corresponding to the line two lines ahead of the present line are read out from the memory, the data corresponding to the present line are written to storage locations from which the data have been read out. Consequently, it is possible to perform processing using data corresponding to three lines using a line memory having a capacity for two lines.

Image data processing apparatus having line memory

Data ID obtained by making analog-to-digital conversion of an output of an image sensor or the like is subjected to shading correction, to obtain correction data SOUT. The correction data SOUT is found by the following equation using white reference data WST and black reference data BST: ##EQU1## where K is a coefficient.

Shading correcting method and shading correcting apparatus

A plurality of bare semiconductor IC chips are mounted on a base substrate. The base substrate and IC chips are sealed in a package to constitute a multichip module. Diodes are disposed on the base substrate so that an end of each diode is connected to a terminal for connecting each IC chip with said base substrate and the other end thereof is connected to a prescribed voltage. As a result, it is possible to inspect the base substrate by contacting probes only with a connecting pad between the base substrate and a package, to reduce the number of pins of a probe card, to produce a cheap probe card and to reduce a rate of imperfect contact between the probe card and an inspecting pad.

Base substrate of multichip module and method for inspecting the same

An apparatus for testing a semiconductor integrated circuit includes a plurality of probe lines and a plurality of sense lines which intersect each other to thereby define a plurality of intersections thereby as electrically isolated from each other. An electronic switch device is provided for each intersection for producing a multilevel signal, on an associated sense line, having one of a predetermined number of voltage levels corresponding to various combinations definable by a predetermined number of binary numbers supplied to test points from logic elements to be tested. In a four test point embodiment, four test points are arranged such that each test point is located in a corresponding one of four quadrants defined by a pair of probe and sense lines intersecting each other. Preferably, the integrated circuit is in the form of a gate array.

Testing integrated circuits by consolidating a plurality of digital

Partial images each constituting a predetermined matrix are sequentially taken out, and density data corresponding to pixels constituting the matrix are subjected to correction. The correction of the density data is so made as to respectively add density correcting values predetermined to correspond to pixel positions in the matrix to the density data. Consequently, the density data corresponding to the pixels constituting the matrix are considerably varied. Therefore, in a binary image obtained by subjecting the partial image constituting the matrix to halftone processing, the density of a document image is sufficiently reproduced.

Apparatus for reproducing image densities using pixel processing and

The present invention provides a half-tone image processing method utilizing an error diffusion technique which allows for the density adjustment of a half-tone image to be reproduced. When the density of an object pixel is converted into binary-coded data, a binary-coding object value is first calculated by adding a density value of the object pixel to an error sum of binary-coding errors distributed to the object pixel from peripheral pixels around the object pixel. Then, the binary-coding object value is compared with a threshold value TH for judging whether the object pixel is a black pixel or a white pixel. The binary-coding object value is also compared with a reference value GSLVB or GSLVW which can be variably set for the calculation of a binary-coding error HG of the object pixel. The level of the binary-coding error HG can be adjusted by variably setting the reference values GSLVB and GSLVW. Thus, the density adjustment of a half-tone image can be realized.

Image processing method utilizing error diffusion technique

A circuit according to the present invention has an input image processing circuit 11 and an image output processing circuit 12 which are asynchronously operated and a shared memory 18. In addition, it has a memory access signal switching circuit 110. The input image processing circuit 11 and the image output processing circuit 12 access the memory 18 in synchronization with the same memory access synchronous clock SYSCLK, and the access right of the image output processing circuit 12 precedes the access right of the input image processing circuit 11. If one cycle of the processing operation of the input image processing circuit 11 is set longer than the sum of the maximum time period during which the input image processing circuit 11 accesses the memory 18 and the maximum time period during which the image output processing circuit 12 accesses the memory 18, the access to the memory 18 by the input image processing circuit 11 and the access to the memory by the image output processing circuit 12 are not overlapped with each other.

Image data processing circuit and method of accessing storing means for

An apparatus for testing a semiconductor integrated circuit by using probe lines and sense lines, has a selection device for applying a selective signal in sequence to one of the probe lines, and electronic switch devices incorporated in the integrated circuit so that the electronic switch devices and intersections, where the probe lines and sense lines intersect each other, are in one-to-one correspondence and the electronic switch devices can feed signals to their corresponding sense lines in response to selective signals applied to the probe lines. Each electronic switch device is connected to test points in the integrated circuit and connected to its corresponding sense line. Many level quantization devices are provided for generating many-level quantized signal, corresponding to one of combinations of binary signals on the test points connected to the electronic switches of each electronic switch device, to its corresponding sense line, and two-level quantization devices convert the many-level quantized signal, generated on each sense line, to reproduced binary signals corresponding to the one of combinations of the binary signals on the test points.

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Toyonaka, Japan

Hideo Azumai