Fujitsu Corporation

Hideo Abe

Kenji Fukuda

Yasuo Tezuka

Satoshi Nemoto

Yuji Obana

Susumu Kojima

Kazuto Nishimura

Takashi Kuwabara

Toru Okada

Hiroshi Tomonaga

Masahiro Shioda

Kazunori Suzuki

Tetsuo Yamaguchi

Hideaki Mochizuki

Katsuichi Ohara

Hiroyuki Asano

Hiromichi Makishima

Tsutomu Chikazawa

Yoshiyasu Tsuruoka

Yoshio Tamura

Koichi Sugama

Takashi Kaiga

Yukio Katayanagi

Ryuji Kayama

Kenichi Yajima

Akio Shinohara

Kazuhiro Yasuno

Masayuki Kawakami

Hidenori Sugai

Yuichiro Chikamatsu

Takeshi Harada

Yuichirou Chikamatsu

Mitsunari Takahashi

Toshiaki Ookubo

An apparatus includes a first switch circuit in an active mode and a second switch circuit in a standby mode. The apparatus receives high-priority packets and low-priority packets. Each switch circuit stores the high-priority packets and the low-priority packets into first and second buffers, respectively. The each switch circuit performs packet-readout processing reading out a packet from the first and second buffers where the packet-readout processing is performed on the first buffer on a priority basis. The apparatus controls the first switch circuit so that a back-pressure time for the high-priority packets becomes longer with increasing amount of data transmitted by the high-priority packets, when a low-priority packet outputted from the first switch circuit is determined to be a packet that has been received at a first time that is later than a second time at which another low-priority packet outputted from the second switch circuit has been received.

Apparatus and method for switching a packet

A signal processing circuit for controlling reading of segment data from a buffer in which a plurality of segment data generated by dividing a frame and received via a plurality of switches which direct each of the segment data to a designated destination are stored, comprises: a start detecting unit which detects a starting segment representing the first transmitted segment data to the switch among the segment data received after the buffer has emptied; a transmission time acquiring unit which acquires a transmission time at which the starting segment was transmitted to the switch; and a read timing control unit which determines, based on the transmission time, a read timing for reading the segment data from the buffer.

Signal processing circuit, interface unit, frame transmission apparatus, and segment data reading method

A device including: a receiving unit receiving a packet; a packet determining unit determining whether the received packet is a head fragment packet or an intermediate or last fragment packet; a search control unit using search data registered previously for searching for packet information and search data used for identifying the same fragment of the fragment packet on the same search address; and an assembly processing unit assembling the fragment packets, wherein the search control unit extracts a fragment identifier from the head fragment packet and registers the fragment identifier as the search data on the same search address as the search address of the search data registered previously for searching for the packet information and extracts the fragment identifier of the intermediate fragment packet or the last fragment packet, makes a search in a way that uses the fragment identifier as search target data, and assembles the fragment packets.

Communication device

In a jitter correction method and circuit, combination data combined by adding, to referenced data, an end bit of dataclock prior to and a head bit of dataclock subsequent to the referenced data is sequentially generated. Each bit of the combination data is sequentially referred. When a change between a referenced bit and a bit directly adjoining the referenced bit is detected, and when a number of references reaches a multiplication number of the oversampling and a change between at least three adjoining bits including the referenced bit is not detected, change position display data regarding the directly adjoining bit as a change bit of the referenced data is generated and the number of references is initialized. When the change is not detected and the number of references does not reach the multiplication number, the number of references is incremented. All the change bits are extracted from the referenced data and the change position display data, and a data reproduction is performed corresponding to the multiplication number.

Jitter correction method and circuit

A transmission device in which a bus of a central processing unit is used to synchronize timing signals between units, thereby restraining enlargement in scale of wiring. A reference signal generator generates a reference signal. A reference signal receiver is mounted on a unit set as an active or standby unit and receives the reference signal. A timing signal generator divides the frequency of the received reference signal by means of a frequency divider/counter to generate a timing signal. A count holder holds the count value of the frequency divider/counter. The bus connects the units and the central processing unit. A count receiver receives, via the bus, the count value from the count holder of the active unit. A count updater updates the count value of the frequency divider/counter to the count value received by the count receiver.

Device for synchronizing between an active unit and a standby unit

The present invention provides a method of high speed assemble process capable of dealing with long packets with effective buffer memories usage. A processing method of fragmented packets in packet transfer equipment for transmitting and receiving packet data between terminals through network, includes, receiving fragmented packets, identifying whether the received packet is a packet fragmented into two from original, or a packet fragmented into three or more, for the packet identified as fragmented into two, storing the two fragmented packets into assembly buffer in fragmentation order, on basis of the respective offset values in the packets, and reading out from top, and for the packet fragmented into three or more, chain-connecting the assembly buffers and storing the packets therein in reception order, reading out the packets after deciding the order by comparing chain information and offset values of the fragmented packets within the chain, and then reassembling the packets.

Processing method of fragmented packet and packet transfer equipment using the same

The present invention relates to a relay device enabling efficient management of a voice message and a caller to wait for transmission of the voice message in a short time. The relay device is located at a boundary between an existing telephone network and an IP network, converts and relays a voice signal and an IP packet. The relay device comprises a receiving unit receiving voice source data into which a voice message is digitized, a packet processing unit converting the received voice source data into a voice source data packet as the IP packet, a storage unit storing the converted voice source data packets, and a transmitting unit transmitting, when transmitting a designated voice message to a designated destination, the voice source data packet corresponding to the designated voice message among the stored voice source data packets.

Relay device and method

Packet buffer equipment in which a buffer and time for packet assembly is utilized for packet header analysis and addition processing to obtain increased efficiency. The equipment aims to receive virtual channel (VC)-multiplexed ATM cells to assemble into a packet on a VC basis maintaining each received cell, to output on a packet basis. As an embodiment, cells are assembled into a packet by storing cells from the top cell to the end cell into a packet buffer memory consisting of a plurality of cell buffers to store cells. Also, a sequence controller is provided for detecting the write completion of a new header cell, and for connecting a packet in packet-under-assembly queue constituted by under-assembly pointer into an output-wait queue.

Packet buffer equipment

The present invention provides a packet transfer system for use in an ATM network, which can realize a high-speed packet transfer by implementing a packet transfer process by hardware and also can enhance the throughput of the packet transfer process implemented by software. This packet transfer system comprises a hardware processing portion, which a memory, a packet assembling portion for causing the memory to store a packet assembled from an ATM cell received from a main circuit or an expansion circuit, a higher layer processing portion for performing higher layer processing portion according to header information sent from the packet assembling portion, and a packet determining/transmitting portion for transmitting a packet, which is determined according to a result of the higher layer processing in the higher layer processing portion as required to undergo packet processing, to an expansion circuit and for transmitting a packet, which is determined according to the result of the higher layer processing as not required to undergo packet processing, in a form of an ATM cell to a main circuit. The packet transfer system may further comprises a software processing portion, which has a second memory, a cell assembling/disassembling portion for assembling the ATM cell received from the expansion circuit into a packet, for causing the second memory to store the assembled packet, for reading the packet stored in the second memory and for transmitting the read packet in the form of an ATM cell to the expansion circuit, a packet processing portion for performing packet processing on a packet, which is received in the second memory, by software.

Packet transfer system

An ATM cell bridge apparatus and a cell bridging method as well as an information transmission system having a cell bridge apparatus by which a cell can be outputted in accordance with a priority degree even during multicast processing. The ATM cell bridge apparatus includes a buffer unit for storing cell data of input cells, a buffer control unit for controlling writing and reading out of the cell data into and from the buffer unit, a cell production control unit for managing multicast information of the cell data read out from the buffer unit by the buffer control unit and producing a cell to be outputted from header information of the cell data, and a cell outputting unit for outputting the cell produced by the cell production control unit and issuing a cell data readout request to the buffer control unit.

Cell bridge apparatus and cell bridging method as well as information transmission system having cell bridge apparatus

A communication unit which transmits packets in the form of ATM cells, includes a packet buffer part receiving Virtual Channel (VC)-multiplexed ATM cells from an input line, judging a packet type, converting a header and assembling a packet, a protocol processing part receiving and processing a protocol packet output from the packet buffer part when the packet type of the packet assembled in the packet buffer part is the protocol packet which is used for communication control, and a packet output scheduling part, including a scheduler which carries out an arbitration when an output request generated upon completion of a reception of a user packet from the packet buffer part and an output request generated upon ending of a process from the protocol processing part are received, and selects and outputs to an output line the user packet or the protocol packet based on the arbitration.

Communication unit having packet multiplexing function

A data processing system having one or more processor modules and a plurality of shared memory busses to increase its total system performance. Processor modules send bus requests to a bus arbiter, when they attempt to make access to shared memories or memory-mapped peripheral control modules. When such memory access requests are received, the bus arbiter checks the availability of each bus that will be used to reach the requested memories, and send bus grant signals to the requesting processor modules after resolving conflicts, if any. Since the system provides separate paths to reach the individual shared memories, two or more processor modules can be granted their access requests at the same time.

Multiprocessor system with multiple memory buses for access to shared memories

Disclosed is an integrated circuit device. According to the present invention, an integrated circuit device comprises: a high frequency electronic circuit having a first enhancement transistor, to the gate of which, at least, a bias voltage is applied; and a bias circuit, including a second enhancement transistor formed on a substrate on which the first enhancement transistor is formed, and first, second and third resistors connected in series between a positive power source and a power source ground, in which a connection point of the first and the second resistors is connected to a drain of the second enhancement transistor, a connection point of the second and the third resistors is connected to a gate of the second enhancement transistor, and voltages at the connection point of the second resistor and the third resistor or at a terminal which is closer to the power source ground is applied as a bias voltage to the high frequency electronic circuit.

Integrated circuit device having a bias circuit for an enhancement

Disclosed is a variable gain semiconductor circuit enjoying a low insertion loss, good distortion characteristic, and large variable gain range. The variable gain semiconductor circuit comprises: a first kind of variable gain circuit that inputs an input signal and changes a gain on the basis of a first control signal; a second kind of variable gain circuit, installed in a stage succeeding the first kind of variable gain circuit, for changing a gain on the basis of a second control signal; and a control signal producing unit for producing the first and second control signals using an attenuation value control signal. When the attenuation value control signal falls within one of two variation ranges instructing a large gain, the control signal producing unit produces the first and second control signals so that the first kind of variable gain circuit decreases a gain according to the variation of the attenuation value control signal, and the second kind of variable gain circuit produces a constant gain. When the attenuation value control signal falls within the other variation range instructing a small gain, the control signal producing unit produces the first and second control signals so that a decrease in gain produced by the first kind of variable gain circuit is saturated and the gain remains unchanged, and a gain produced by the second kind of variable gain circuit decreases according to the variation of the attenuation value control signal.

Growing community of inventors

Kawasaki, Japan

Hideo Abe