Nec Corporation

Nec Compound Semiconductor Devices, Ltd.

Hidenori Shimawaki

Masahiro Tanomura

Yasuhiro Okamoto

Hironobu Miyamoto

Takashi Inoue

Yuji Ando

Tatsuo Nakayama

Kenichi Maruhashi

Yasuhiro Murase

Kazuki Ota

Kensuke Kasahara

Akio Wakejima

Takaki Niwa

Kohji Matsunaga

Naoto Kurosawa

Katsumi Yamanoguchi

Fumio Harima

Yosuke Miyoshi

Kouji Azuma

Takashi Ishigaki

Koji Azuma

Yousuke Miyoshi

A power amplifier of the present invention comprises MOS transistor () having a gate length of 180 nm or less, and output matching circuit () connected to a drain terminal of MOS transistor (). Also, MOS transistor () is applied with voltage Vd_n normalized by a voltage value allowable in a DC state as a drain-source voltage, where Vd_n is in a range of 0.5 to 0.9. ZL (=RH+j&#xb7;XL) represents a value equal to a load impedance when viewing the output matching circuit () from the drain terminal normalized by gate width W (mm) of MOS transistor (), and a real part (RL) of the ZL is RL&#x3e;0.64&#xd7;Vd_n+0.19 (&#x3a9;&#xb7;mm), and RL&#x3c;0.64&#xd7;Vd_n+1.73 (&#x3a9;&#xb7;mm).

Power amplifier, and method of controlling power amplifier

A radio communications device includes a transmitter, a receiver, a propagation detecting unit, and a symbol rate setting unit. The receiver has a plurality of antennas, a plurality of transmitting circuits, and a transmission signal processing circuit. The transmission signal processing circuit has a modulator, and modulates data input transmission data in modulator to output the modulated data as transmission signal to the transmitting circuits. The receiver has a plurality of antennas, a plurality of receiving circuits, and a reception signal processing circuit. The reception signal processing circuit has a demodulator, demodulates reception signals input from the receiving circuits in demodulator to generate reception data. The propagation detecting unit detects propagation state of radio waves. The symbol rate setting unit selects a symbol to be communicated from a plurality of symbol rates based on the detected propagating state and sets the selected symbol rate to the modulator and to the demodulator.

Radio communication device

A field effect transistor () exhibiting good performance at high voltage operation and high frequency includes a first field plate electrode () and a second field plate electrode (). The second field plate electrode includes a shielding part () located in the region between the first field plate electrode and a drain electrode (), and serves to shield the first field plate electrode from the drain electrode. When in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region where the second field plate electrode () overlap the upper part of a structure including the first field plate electrode and a gate electrode () is designated as Lol, and the gate length is Lg, the relation expressed as 0 &#x2266;Lol/Lg&#x2266;1 holds.

Field effect transistor

A field effect transistor includes a layer structure made of compound semiconductor () provided on a semiconductor substrate () made of GaAs or InP, as an operation layer, and employs a first field plate electrode () and a second field plate electrode (). The second field plate electrode includes a shielding part () located in the region between the first field plate electrode and a drain electrode (), and serves to shield the first field plate electrode from the drain electrode. When, in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region, in which the second field plate electrode overlaps the upper part of a structure composed of the first field plate electrode and a gate electrode (), is designated as Lol, and the gate length is Lg, the relation expressed as 0&#x2266;Lol/Lg&#x2266;1 holds.

A semiconductor device includes a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer, which are sequentially laminated on a substrate. It also includes an emitter electrode, a base electrode, and a collector electrode, which are respectively formed on the emitter cap layer, the base layer, and the sub-collector layer. The sub-collector layer is made up of a first sub-collector layer adjacent to the substrate and a second sub-collector layer adjacent to the collector layer. In the area between adjacent device elements, the first sub-collector layer has an element insulating region created by ion implantation, and the second sub-collector layer has a recess-shaped element insulating region.

Semiconductor device and method of manufacturing the same

A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

Heterojunction bipolar transistor and method of producing the same

A heterojunction bipolar transistor has a raised breakdown voltage and restrains the rising characteristic of I-Vcharacteristic from degrading. The collector region includes first, second, and third collector layers of semiconductor. The first collector layer is made of a doped or undoped semiconductor in such a way as to contact the sub-collector region. The second collector layer is made of a doped or undoped semiconductor having a narrower band gap than the first collector layer in such a way as to contact the base region. The third collector layer has a higher doping concentration than the second collector layer in such a way as to be located between or sandwiched by the first collector layer and the second collector layer.

Heterojunction bipolar transistor and semiconductor integrated circuit device using the same

A semiconductor device of the present invention includes a systematic structure layer of first conductivity type and having a systematically arranged structure. The systematic structure layer is formed on a collector contact layer of first conductivity type, which is connected to collector electrodes. A compensation layer of first conductivity type is formed on the systematic structure layer. A collector layer of first conductivity type is formed on the compensation layer. A base layer is formed on the collector layer and connected to base electrodes. An emitter layer is formed on the base electrode and connected to an emitter electrode. The semiconductor device reduces collector resistance and thereby improves reliability.

Semiconductor device and method of producing the same

A heterojunction bipolartansistor is fabricated on a semi-insulating substrate, and has a mesa structure, wherein an emitter signal line of titanium-platinum-gold alloy is held in contact with the collector layer as well as the emitter layer for forming a Schottky barrier diode connected between the emitter and the collector so that surge current flows before damage of the p-n junction of the heterojunction bipolar transistor.

Compound semiconductor device having diode connected between emitter and collector of bipolar transistor

The bipolar transistor includes an emitter layer at least a part of which is composed of AlGaAs, a collector layer at least a part of which is composed of GaAs, a base contact layer disposed in at least a part of an area between a base electrode and a base layer, and a base layer at least a part of which is composed of an InGaAs graded layer in which the concentration of In gradually increases from an emitter-base junction towards a base-collector junction.

Bipolar transistor including a compound semiconductor

A heterojunction bipolar transistor has an n-type emitter layer of aluminum gallium arsenide and a beryllium doped base layer forming a heterojunction together with the n-type emitter layer, and the base layer is associated with a heavily doped carbon doped base region so that the beryllium content is restricted below the critical value for preventing the emitter layer from undesirable beryllium diffusion.

Heterojunction bipolar transistor having base structure for improving

On a semi-insulating substrate, an emitter layer (or a collector layer), a base layer, a compound semiconductor layer containing In and a collector layer (or an emitter layer) are provided. The collector layer (or the emitter layer) is patterned to form a collector region (or an emitter region). When the base surface is revealed by a reactive ion beam etching, the etching will be stopped at the compound semiconductor layer that contains In. Consequently, the nonuniformity in the base resistance that depends on the thickness of the base lead-out region can be reduced.

Method of fabricating a heterojunction bipolar transistor

Heterojunction bipolar transistor with improved base layer

A method of selective epitaxial growth for compound semiconductor includes the steps of forming a layer of group IV element semiconductor, such as Ge, with a predetermined pattern on a compound semiconductor substrate and forming a compound semiconductor layer selectively on the compound semiconductor substrate by alternately supplying a gas of compound containing a group III or II element, such as trimethylgallium, triethylgallium and triisobutylaluminum, and a gas of compound containing a group V or VI element, such as AsH.sub.3, onto both surface of the layer of group IV element semiconductor and the compound semiconductor substrate. Another semiconductor layer of group IV element semiconductor or compound semiconductor may be formed on the layer of group IV element semiconductor by organometallic vapor phase epitaxy or MBE.

Growing community of inventors

Tokyo, Japan

Hidenori Shimawaki