Sumitomo Electric Industries, Limited

Hidenori Mikami

Naoki Matsumoto

Keiji Ishibashi

Yusuke Yoshizumi

Seiji Nakahata

Akihiro Hachigo

Fumitake Nakanishi

Yuki Hiromura

Yoshiyuki Yamamoto

Koji Uematsu

Yuki Seki

Takuya Yanagisawa

Sayuri Yamaguchi

Hideki Osada

Provided are a group III nitride composite substrate having a low sheet resistance and produced with a high yield, and a method for manufacturing the same, as well as a method for manufacturing a group III nitride semiconductor device using the group III nitride composite substrate. A group III nitride composite substrate includes a group III nitride film and a support substrate formed from a material different in chemical composition from the group III nitride film. The group III nitride film is joined to the support substrate in one of a direct manner and an indirect manner. The group III nitride film has a thickness of 10 &#x3bc;m or more. A sheet resistance of a group III-nitride-film-side main surface is 200 &#x3a9;/sq or less.

Group III nitride composite substrate and method for manufacturing the same, and method for manufacturing group III nitride semiconductor device

A group III nitride composite substrate includes a support substrate and a group III nitride film. A ratio s/mof a standard deviation sof the thickness of the group III nitride film, to a mean value mof the thickness thereof is 0.001 or more and 0.2 or less, and a ratio s/mof a standard deviation sof an absolute value of an off angle between a main surface of the group III nitride film and a plane of a predetermined plane orientation, to a mean value mof the absolute value of the off angle thereof is 0.005 or more and 0.6 or less. Accordingly, there is provided a low-cost and large-diameter group III nitride composite substrate including a group III nitride film having a large thickness, a small thickness variation, and a high crystal quality.

Group III nitride composite substrate and method for manufacturing the same, laminated group III nitride composite substrate, and group III nitride semiconductor device and method for manufacturing the same

A nitride semiconductor device includes a main surface and an indicator portion. The main surface is a plane inclined by at least 71&#xb0; and at most 79&#xb0; in a [1-100] direction from a (0001) plane or a plane inclined by at least 71&#xb0; and at most 79&#xb0; in a [&#x2212;1100] direction from a (000-1) plane. The indicator portion indicates a (&#x2212;1017) plane, a (10-1-7) plane, or a plane inclined by at least &#x2212;4&#xb0; and at most 4&#xb0; in the [1-100] direction from these planes and inclined by at least &#x2212;0.5&#xb0; and at most 0.5&#xb0; in a direction orthogonal to the [1-100] direction.

Nitride semiconductor substrate

A nitride semiconductor substrate having a main surface serving as a semipolar plane and provided with a chamfered portion capable of effectively preventing cracking and chipping, a semiconductor device fabricated using the nitride semiconductor substrate, and a method for manufacturing the nitride semiconductor substrate and the semiconductor device are provided. The nitride semiconductor substrate includes a main surface inclined at an angle of 71&#xb0; or more and 79&#xb0; or less with respect to the (0001) plane toward the [1-100] direction or inclined at an angle of 71&#xb0; or more and 79&#xb0; or less with respect to the (000-1) plane toward the [&#x2212;1100] direction; and a chamfered portion located at an edge of an outer periphery of the main surface. The chamfered portion is inclined at an angle &#x3b8;or &#x3b8;of 5&#xb0; or more and 45&#xb0; or less with respect to adjacent one of the main surface and a backside surface on a side opposite to the main surface. Accordingly, cracking and chipping occurring from the edge of the outer periphery of the nitride semiconductor substrate can be effectively suppressed.

Nitride semiconductor substrate, semiconductor device, and methods for manufacturing nitride semiconductor substrate and semiconductor device

A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 &#x3bc;m-10 &#x3bc;m thick edge process-induced degradation layer.

Nitride semiconductor wafer having a chamfered edge

Method of processing of nitride semiconductor wafer, nitride semiconductor wafer, method of producing nitride semiconductor device and nitride semiconductor device

Nitride semiconductor wafer

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Itami, Japan

Hidenori Mikami