Panasonic Liquid Crystal Display Co., Ltd.

Hitachi Displays, Ltd.

Japan Display Inc.

Pasona Knowledge Partner Inc.

Hidenori Kikuchi

Yasuhiro Tanaka

Yukihide Ode

Hironobu Isami

Haruhisa Iida

Takashi Kato

Kazuhiko Tsuda

Katsuji Tanaka

Yoichi Yasui

Takenori Yaguchi

Takaaki Kitada

Naoki Terasawa

Hiroshi Watanabe

Shinji Yasukawa

Hiroaki Sato

Katsuyuki Awazu

A liquid crystal display device includes a first glass substrate, a second glass substrate, a first liquid crystal layer disposed between the first glass substrate and the second glass substrate, a third glass substrate, a fourth glass substrate, a second liquid crystal layer disposed between the third glass substrate and the fourth glass substrate, a first polarizing plate formed on the first glass substrate, a second polarizing plate formed on the third glass substrate, and a bonding layer disposed between the first glass substrate and the third glass substrate. In planar view, the bonding layer is disposed outside the first polarizing plate and the second polarizing plate, a surface on the bonding layer bonds to the first glass substrate, and a surface on the bonding layer bonds to the third glass substrate.

Liquid crystal display device

A display device () comprising: a display panel (); a middle frame () holding the display panel (); and an upper frame () covering the display panel () from a display surface side. The middle frame () includes a placing portion () on which a peripheral portion of the display panel () is placed, the upper frame () includes a frame portion (), which is disposed opposite to the peripheral portion of the display panel (). A distance between the placing portion () and the frame portion (), which are disposed opposite to each other on corner portions of the display panel (), differs from a distance between the placing portion () and the frame portion (), which are disposed opposite to each other on a central portion of the display panel ().

Display device

There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for delay direction and width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.

Display apparatus

There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and multiple drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit for generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for a delay direction and a delay width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.

A display device includes a display panel having a plurality of video lines, and a drain driver receiving n-bit display data, and connected to the plurality of video lines. The drain driver includes a gray-scale voltage generating circuit which generates M (M&#x3c;2) pieces of gray-scale voltages, a decoder circuit which selects two gray-scale voltages from the M pieces of gray-scale voltages based on upper-order bits of the n-bit display data, an operational amplifier which includes k (k&#x2267;3) pieces of non-inverting input terminals and one inverting input terminal connected to an output terminal of the operational amplifier, and a switching circuit which selects the two gray-scale voltages of the decoder circuit, and applies the two gray-scale voltages to the k pieces of non-inverting input terminals of the operational amplifier based on lower-order m (n&#x3e;m&#x2267;2) bits of the n-bit display data.

The present invention provides a display device which can suppress the increase of a chip size while reducing the number of transistors of a decoder circuit compared to the prior art. Assuming m (m being an integer of 2 or more) as a lower-order bit in accordance with n-bit display data, a drive part includes a gray-scale voltage generating circuit which generates M pieces of gray-scale voltages where the gray scale number with respect to the gray-scale voltages is discontinuous, a decoder circuit which selects two neighboring gray-scale voltages out of M pieces of gray-scale voltages based on data of upper-order (n-m) bits in accordance with n-bit display data, and an output amplifying circuit which generates gray-scale voltages between two gray-scale voltages from two gray-scale voltages selected by the decoder circuit based on the data of lower-order m bits in accordance with n-bit display data and outputs the gray-scale voltages to the video lines.

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Chosei, Japan

Hidenori Kikuchi