Sony Semiconductor Solutions Corporation

Hidenobu Tsugawa

Tomoharu Ogita

Hiroshi Takahashi

Ryoichi Nakamura

Kiichi Ishikawa

An imaging device according to an embodiment of the present disclosure including a first chip; a support substrate; and a second chip. The support substrate includes an excavated portion in a region opposed to the first chip. The excavated portion has a shape of a recess or a shape of a hole. The second chip is disposed in the excavated portion of the support substrate. The second chip is electrically coupled to the first chip. At least one of the first chip or the second chip has a photoelectric conversion function.

Imaging device

The present technology relates a solid-state imaging element, an electronic apparatus, and a semiconductor device each of which enables deterioration of electrical characteristics in a well region of a semiconductor element formed in a thinned semiconductor substrate to be restrained. A solid-state imaging element as a first aspect of the present technology is a solid-state imaging element constituted by laminating semiconductor substrates in three or more layers, in which of the laminated semiconductor substrates, at least one sheet of the semiconductor substrate is thinned, and an impurity region whose carrier type is the same as that of the thinned semiconductor substrate is formed between a well region and a thinned surface portion in the thinned semiconductor substrate. The present technology can, for example, be applied to a CMOS image sensor.

Solid-state imaging element, electronic apparatus, and semiconductor device

The present disclosure relates to a semiconductor device, a manufacturing method, an imaging element, and an electronic device capable of reducing manufacturing steps in a stacked structure obtained by stacking two or more semiconductor substrates. The semiconductor device has a stacked structure obtained by stacking at least a first semiconductor substrate in which a first wiring layer is stacked on a first semiconductor layer and a second semiconductor substrate in which a second wiring layer is stacked on a second semiconductor layer. Then, a through via which electrically connects the first semiconductor substrate and the second semiconductor substrate to each other and penetrates at least the first semiconductor layer is formed in an embedded oxide film formed when element isolation of a semiconductor element formed in the first semiconductor layer is performed. The present technology is applicable to, for example, a stacked semiconductor device.

Growing community of inventors

Kanagawa, Japan

Hidenobu Tsugawa