Kioxia Corporation

Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Hidenobu Nagashima

Masayuki Akou

Shingo Nakajima

Ryota Asada

Masaki Kondo

Hiroshi Akahori

Yoshiko Kato

Kiyohito Nishihara

Shigeo Kondo

Takashi Ichikawa

Kazuaki Iwasawa

Mitsuhiko Noda

Akira Yotsumoto

Daina Inoue

Yingkang Zhang

According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.

Semiconductor memory device

According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.

Semiconductor device and method of manufacturing the same

In one embodiment, a semiconductor memory device includes a substrate, and device regions formed in the substrate to extend in a first direction which is parallel to a principal plane of the substrate. The device further includes select gates disposed on the substrate to extend in a second direction which is perpendicular to the first direction, and a contact region provided between the select gates on the substrate and including contact plugs disposed on the respective device regions. Further, the contact region includes partial regions, in each of which N contact plugs are disposed on N successive device regions to be arranged on a straight line being non-parallel to the first and second directions, where N is an integer of 2 or more. Further, the contact region includes the partial regions of at least two types whose values of N are different.

According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.

Nonvolatile memory device

A semiconductor storage device includes an interlayer insulating film provided between select gate electrodes, a first fill material extending along upper portions of memory cell gate electrodes so as to cover air gaps residing between the memory cell gate electrodes, the first fill material extending along sidewalls of the select gate electrodes and sidewalls of the interlayer insulating film so as to define a recess above the first fill material extending along the sidewalls of the select gate electrodes and the sidewalls of the interlayer insulating film, a second fill material filling the recess above the first fill material, and a plurality of contacts formed through the interlayer insulating film, the contacts physically contacting each of device areas formed in a semiconductor substrate.

Semiconductor storage device including a memory cell structure

According to one embodiment, a nonvolatile semiconductor memory device includes memory transistors, an interlayer insulating film, a peripheral transistor and a sidewall. The memory transistors are formed on a semiconductor substrate. Each of the memory transistors includes a first stack gate which includes a floating gate electrode, a second gate insulating film, and a control gate electrode. The interlayer insulating film is formed between the first stack gates. The interlayer insulating film includes a first air gap. The peripheral transistor is formed on the substrate. The peripheral transistor includes a second stack gate which includes a first gate electrode, a third gate insulating film, and a second gate electrode. The sidewall is formed on a side surface of the second stack gate and includes a second air gap. An upper end of the second air gap is located at a position lower than the third gate insulating film.

Growing community of inventors

Yokkaichi, Japan

Hidenobu Nagashima