Nec Corporation

Nec Electronics Corporation

Hidenobu Miyamoto

Tatsuya Usami

Koichi Ohto

Kazuyoshi Yoshida

Noboru Morita

Yoichi Sasaki

Koji Arita

Masayoshi Tagami

Ken Inoue

Yasuhiko Ueda

Hideaki Kawamoto

Makoto Sekine

Eiji Ikawa

A semiconductor devicecomprises a SiCN filmformed on a semiconductor substrate (not shown), a first SiOC filmformed thereon, a SiCN filmformed thereon, a second SiOC filmformed thereon, a SiOfilmand a SiCN filmformed thereon. The first SiOC filmhas a barrier metal layerand viaformed therein, and the second SiOC filmhas a barrier metal layerand wiring metal layerformed therein. Carbon content of the second SiOC filmis adjusted larger than that of the first SiOC film. This makes it possible to improve adhesiveness of the insulating interlayer with other insulating layers, while keeping a low dielectric constant of the insulating interlayer.

Method of manufacturing a semiconductor device

Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on a substrate in the order mentioned, the second hard mask being formed to have a trench pattern. At least a light absorbing sacrificial film, which has an etching rate different from that of a photoresist and is removable by use of a stripping solution, is formed on the semiconductor substrate in such a manner that the overall surface thereof will be flat. The photoresist is formed on the light absorbing sacrificial film and has an aperture pattern whose opening width is less than that of the trench pattern. At least the light absorbing sacrificial film, the first hard mask and the second interlayer film are etched selectively, one after the other, using the photoresist as an etching mask.

Semiconductor device and method of manufacturing same

Semiconductor device and method of manufacturing a semiconductor device

According to a fabrication method of a semiconductor device, differing areas of metal interconnect layers,and,are formed on top of interlayer base layer,. An HSQ layer,is then deposited over them. A plasma SiO,is then deposited on top of the HSQ film,. Afterwards, the top surface of the plasma SiO,film,is subjected to the CMP process so that its surface can be smoothed. A photoresist film,is deposited on top of the SiO,film,and then patterned for a subsequent step of making via holes. Afterwards, the insulation film,and HSQ film,are selectively etched so as to dig via holes,so that the bottoms,of the via holes,respectively end at the top surfaces of the interconnect layers,and,. This etching is performed using a mixture of a fluorine-based gas and a hydrogen-based gas.

Method of manufacturing semiconductor device with via holes reaching interconnect layers having different top-surface widths

A polysilicon film is deposited on a semiconductor substrate. A PSG film that can be removed from a material that composes field oxide films and sidewalls of a side surface portion of a gate electrode with a satisfactory selective ratio is deposited on the resultant semiconductor substrate. After the deposited films are processed as a gate electrode, the sidewalls are formed on the side surface portion of the gate electrode. Thereafter, the PSG film is selectively removed and the front surface of the polysilicon film, which composes the gate electrode, is exposed. Tungsten films are deposited on the front surfaces of the polysilicon film and source and drain region formed on the semiconductor substrate. After the SiON film is formed on the resultant semiconductor substrate, contact holes and then contacts are formed on the SiON film.

Semiconductor apparatus and fabrication method thereof

A dielectric member is provided at the upper portion of a grounded vacuum reaction vessel. Other portion of the vacuum reaction vessel is grounded. A flow path is formed within the dielectric member. The flow path is covered with a conductive member and an insulation member. The conductive member is grounded at the same voltage as the vacuum reaction vessel. Also, a temperature measuring element is buried within the dielectric member. The temperature measured by the temperature measuring element is fed back so that the temperature of the hot insulation medium is controlled. Thus, the temperature of the dielectric member is maintained constant within a range of 60.degree. to 160.degree. C.

Plasma processing apparatus

An apparatus for generating plasma, includes a cylindrical vacuum chamber made of dielectric substance, the chamber being open only at a bottom thereof and having a height of 50 mm or smaller, at least one antenna coil disposed around the chamber for receiving high frequency power therein, and at least one electromagnetic coil disposed around the antenna coil. The cylindrical vacuum chamber may be replaced with a plate made of a dielectric substance. The apparatus is operative to carry out photoresist using etching without leaving any residue under a high selection ratio to the photoresist. In addition, the etching product does not tend to adhere to the vacuum chamber, and it would be easy to remove etching product from the vacuum chamber, even if the product adheres to the vacuum chamber.

Plasma generating apparatus used for fabrication of semiconductor device

Disclosed herein is a method of manufacturing a semiconductor device, the method including a step of anisotropic-etching of a high-melting-point (or refractory) metal silicide layer by use of a halogen-containing gas using. This halogen-containing gas has a boron trichloride gas as a main component gas and either one of a chlorine gas or a hydrogen bromide gas as an auxiliary or a sub-component gas.

Method for selectively etching polycide layer

A plasma processing apparatus comprises a reaction chamber to hold a high-density plasma and having a dielectric plate window, a spiral coil placed outside the reaction chamber and close to the dielectric window, and a lower electrode which holds a wafer to be processed in place and installed in the reaction chamber facing the dielectric plate. A first radio frequency current supply to the coil, a mechanism for varying the distance between the coil and the dielectric plate window, and a second radio frequency voltage supply to the lower electrode is provided. Excellent uniformity of the ion current density of the plasma and hence etching rate is achieved by making the thickness of a central part of the dielectric plate window thicker than its peripheral parts. Also, the uniformity of the plasma and the etching rate is achieved by making the induction field produced by the coil axially symmetrical about the axial center of the reaction chamber. The etching profile and the material etching selectivity are controlled by moving the coil in the axial direction of the coil.

Plasma processing apparatus for manufacture of semiconductor devices

During etching of semiconductor substrate having a polysilicon layer and a silicide layer on the polysilicon layer by plasma etching to produce a processed semiconductor substrate having a patterned silicide layer and a patterned polysilicon layer, the semiconductor substrate is located on a supporting electrode. The temperature of the electrode is controlled to a predetermined temperature. The predetermined temperature may be, for example, 0.degree. C. The silicide layer is etched into the patterned silicide layer by plasma etching. The semiconductor substrate is placed in closer contact with the supporting electrode. A coolant gas is then supplied to the supporting electrode in order to cool the supporting electrode. The polysilicon layer is etched into the patterned polysilicon layer by plasma etching in order to produce the processed semiconductor substrate.

Etching method for etching a semiconductor substrate having a silicide

A first insulating layer is formed on a semiconductor substrate. A lower metal layer and a upper metal layer are sequentially formed on the first insulating layer, and also, a second insulating layer is formed thereon. Then, a photoresist pattern is formed, and the second insulating layer and the upper metal layer are etched with a mask of the patterned photoresist layer. Then, the patterned photoresist layer is removed, and a sidewall insulating layer is formed on a side of the upper metal layer. Finally, the lower metal layer is etched with a mask of the second insulating layer and the sidewall insulating layer.

Method for manufacturing fine-structured stacked connection layer

A conductive layer is formed on a semiconductor substrate, and is etched so that a side face of the conductive layer is reversely-tapered. Also, a sidewall insulating layer is formed on the side face of the conductive layer. Then, a groove is formed within the semiconductor substrate with a mask of the sidewall insulating layer, and an isolation insulating layer is buried within the groove.

Method for manufacturing semiconductor device having groove-structured

A method of preventing corrosion of aluminum alloys is disclosed, which comprises the steps of coating an aluminum alloy layer on a semiconductor substrate, forming a resist pattern on an aluminum alloy layer, dry etching the aluminum alloy with the resist pattern used as a mask and also using a chlorine-based gas, and subsequently carrying out a plasma process using a blend gas containing oxygen (O.sub.2) and ammonia (NH.sub.3) and a subsequent process of removing the resist using oxygen plasma. Even where there is not only aluminum alloy but an outer or inner layer of TiN, TiW, etc. to be etched, corrosion of the aluminum alloy can be prevented without etching the outer or inner layer at all and also without etching an inner insulating layer at all.

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Tokyo, Japan

Hidenobu Miyamoto