Adv Antest Corporation

Hidenobu Matsumura

Hiroaki Yamoto

Koji Takahashi

Takao Sakurai

Shin Masuda

Noriyuki Masuda

Shusuke Kantake

Toshihiro Sugawara

Takao Seki

An optical testing device for use in testing an optical measuring instrument provides incident light from a light source to an incident object and receives reflected light due to reflection of the incident light at the incident object. The optical testing device includes an incident light receiving section that receives incident light, and a light signal providing section. The light signal providing section provides a light signal to the incident object after a predetermined delay time since the incident light receiving section has received the incident light. A reflected light signal due to reflection of the light signal at the incident object is provided to the optical measuring instrument. The delay time is approximately equal to the time between emission of the incident light from the light source and reception of the reflected light by the optical measuring instrument in the case of actually using the optical measuring instrument.

Optical testing apparatus

A test carrier includes a base member on which a first electronic device under test is able to be temporarily mounted, and a second electronic device which is configured to be used to test the first electronic device. The second electronic device is mounted on the base member, and the second electronic device is able to be electrically connected to the first electronic device.

Test carrier for mounting and testing an electronic device

Provided is a receiving method and a receiving apparatus comprising a multi-strobe generating section that generates a multi-strobe including a plurality of strobes having different phases with respect to a reception signal; an acquiring section that acquires the reception signal using each of the strobes; a detecting section that detects a change position at which a value of the reception signal changes, based on the acquisition result of the acquiring section; and a selecting section that selects, as a reception data value, the value of the reception signal acquired using a strobe at a position shifted by a predetermined phase from the change position. The receiving apparatus may further comprise a reference clock generating section that generates a reference clock having a preset period, and the multi-strobe generating section generates the multi-strobe for each pulse of the reference clock.

Receiving apparatus, test apparatus, receiving method, and test method

A semiconductor integrated circuit design and evaluation system for designing an LSI device under an electric design automation (EDA) environment and for evaluating a test pattern produced based on the CAD data derived in the design stage of the LSI device. The system includes an EDA environment for designing an LSI device and evaluating functions of the designed LSI device by a device logic simulator, a dump file for storing data expressed by an event base obtained by executing the device logic simulation, an LSI tester simulator for generating a test pattern and an expected value pattern in a cycle base, a cycle-event converter for converting the test pattern from the LSI tester simulator in the cycle base to a test pattern of the event base, a first memory for storing the event based test pattern from the cycle-event converter, a second memory for storing the data from the dump file, and a comparator for synchronizing the data stored in the first and second memories by comparing the timing relationship between the two and extracting output data of the device under test from the dump file corresponding to the test pattern from the LSI tester simulator.

Semiconductor integrated circuit design and evaluation system using cycle base timing

A high speed evaluation apparatus for evaluating a test pattern produced for a semiconductor test system or performing a diagnostic test on a design of the semiconductor device, based on logic simulation data produced in a design stage of the semiconductor device through a CAD (computer aided design) process, without using an actual semiconductor test system or a semiconductor device. The apparatus includes an LSI tester simulator for generating a test pattern for testing a semiconductor device and an expected value pattern for comparing the output of the semiconductor device which is responsive to the test pattern, a cycle-event converter for converting the test pattern from the LSI tester simulator in a cycle base form to a test pattern of an event base form, a first memory for storing the event based test pattern from the cycle-event converter, a second memory for storing a predetermined amount of input/output data of the semiconductor device from a dump file storing data resulted from executing a logic simulation on the semiconductor device in the design stage of the semiconductor device under the CAD process, and a comparator for synchronizing the data stored in the first and second memories by comparing the timing relationship between the two and extracting output data of the device under test from the dump file corresponding to the test pattern from the LSI tester simulator.

High speed test pattern evaluation apparatus

A semiconductor integrated circuit evaluation system for evaluating, at high speed, functions of a device under test and a test pattern for testing the device under test without using an actual tester or designed device. The evaluation system includes a test pattern file for storing a test pattern to be applied to a device for testing the device under test, a first memory for storing tester event information by receiving a predetermined amount of test pattern from the test pattern file, a first FIFO (first-in-first-out) for receiving a predetermined amount of the tester event information from the first memory and extracting the tester event information in the order of receiving the same, a second memory for storing device event information by receiving a predetermined amount of event information resulted from logic simulation of the device under test based on design data of the device produced through a computer aided design process, a second FIFO for receiving a predetermined amount of the device event information from the second memory and extracting the device event information in the order of receiving the same, a comparator for comparing the event information from the first FIFO and the second FIFO, and means for generating a comparison result from the comparator.

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Tokyo, Japan

Hidenobu Matsumura