Nec Corporation

Hidenobu Harasaki

Yoichi Katayama

Yukio Endo

Ichiro Tamitani

Kiyoshi Ishiyama

To improve qualities of audio and picture signals by distributing adaptively the code quantities of audio codes and picture codes and by adopting variable rate audio coding. The audio/picture processing apparatus handles audio presence information, audio characteristics information, audio quality information, picture quality information, code quantity distribution information, and line capacity information. A code quantity control means decides the distribution of the audio and picture codes, an audio coding format, and a coding rate, whereby the audio signal and picture signal are coded by a picture encoder and an audio encoder. The outputs from the picture encoder and the audio encoder are multiplexed by a multiplexer in order to transmit a multiplexed bit stream onto the network.

Coding apparatus for audio and picture signals

In a transmission error correction code appending device which receives a variable bit rate signal transmitted at a variable bit rate and having a plurality of information bytes, a transmitting circuit transmits, unless a timer circuit produces a time-out signal, the information bytes to a correction code appending circuit and transmits, when the timer circuit produces the time-out signal, zero bytes to the correction code appending circuit subsequently to the information bytes so that the information bytes and the zero bytes constitute first through N-th data bytes of first through M-th data groups, where each of M and N represents a predetermined plural and natural number. The correction code appending circuit consecutively supplies an interleaver with first through M-th blocks, each having the first through the N-th data bytes and first through P-th error correction code bytes as first through Q-th block bytes, where P represents a prescribed natural number, Q being equal to (N+P). An informing signal producer produces an informing signal when the interleaver receives the first block byte of the first block. The timer circuit produces the time-out signal when the timer circuit times a preselected time interval from a time instant at which the timer circuit receives the informing signal.

Transmission error correction code appending device which can regulate a

An image memory device wherein data necessary for interpolation is read out simply and successively from a frame memory at a time without requiring a complicated timing control circuit to allow interpolation processing to be performed at a high speed. Image data are temporarily stored into a plurality of parallel frame memories having an interleave construction. Conversion addresses for the frame memories are generated based on different conversion rules from a plurality of address decoders and applied in parallel at a time to the frame memories so that data at neighboring points of a coordinate position for an object of interpolation are outputted at a time from the frame memories. The neighboring point data are inputted in parallel at a time, or pipeline inputted, to an interpolation calculation circuit so that coefficients are generated from individual pipelines. Product sum calculation is performed for the coefficients and the neighboring point data.

Image memory device

In a real-time video signal processor for processing an input digital video signal divisible into a succession of principal blocks each of which has at least one scanning line and a time duration shorter than a frame period, each principal block is divided into at least two partial blocks with each scanning line divided into the respective partial blocks. A plurality of signal processing modules are assigned with the respective partial blocks of each principal block, respectively. Responsive to the input digital video signal and an additional digital video signal, the signal processing modules process the respective partial blocks of each principal block into processed signals during the time duration, respectively. Each processed signal comprises a first partial signal used as an output signal of the processor and a second partial signal. A delaying circuit delays the second partial signals derived from the signal processing modules into a delayed signal having a delay equal to a difference between the frame period and the time duration. The delayed signal is used as the additional signal. A plurality of the real-time video signal processors may be connected in cascade to each other. Two memory units may be used instead of the delaying circuit. Readout operation of each principal block from the memory units is controlled by control signals produced by a control signal producing circuit. Principal blocks read out of the memory units are supplied to the signal processing modules.

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Tokyo, Japan

Hidenobu Harasaki