Renesas Technology Corp.

Renesas Electronics Corporation

Hidemoto Tomita

Shigeki Ohbayashi

Yoshiyuki Ishigaki

Akira Hosogane

Nobuyuki Kokubo

Motomu Ukita

Yoji Kashihara

A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element, a second gate wiring element, a first connector, and a second connector. Each memory cellhas first and second sets having a driver transistor, a load transistor, and an access transistor. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.

Semiconductor storage device and method of fabricating the same

A semiconductor memory device includes a memory cell array in which memory cells each having six transistorsandare arranged two-dimensionally on a semiconductor substrate. The semiconductor memory device also includes a plurality of word lines connected to each of the memory cells, and arranged on a parallel to each other along a first direction, a plurality of bit lines connected to each of the memory cells and arranged on a parallel to each other along a second direction perpendicular to the first direction, and at least two gate electrodes provided on the semiconductor substrate such that each of the gate electrodes is connected to at least one transistor of the six transistors, all of the gate electrodesandbeing arranged on the same straight line parallel to the first direction.

Semiconductor memory device

A transistor region for defining a transistor receiving an address signal at a gate thereof is provided in or near a region below an address interconnection line transmitting a corresponding address signal. The corresponding address signal and the gate electrode of the corresponding transistor are connected together by an intermediate interconnection line extending only in the region having the corresponding address interconnection line arranged. Accordingly, a high speed switching of address signals can be achieved.

Semiconductor circuit device with mitigated load on interconnection line

A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element , a second gate wiring element , a first connector , and a second connector . Each memory cell has first and second sets having a driver transistor , a load transistor , and an access transistor . The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.

An address signal is transferred from an address bus transmitting an address from an address generation circuit, to a real address bus connecting to a decoder for decoding an applied address signal, via a branch node, a branch address bus and contacts. The real address bus and the branch address bus are electrically connected at a plurality of points using the contacts. The branch address bus functions as a lining or backing signal line to the real address bus, and a line resistance and line capacitance of the real address bus can be equivalently reduced. A variation in signal propagation delay over an entire decoding circuits is suppressed.

Semiconductor circuit device capable of high speed decoding

A local decoder controlling activation of each word line includes a first transistor connected between first and second nodes, a second transistor connected between a power-supply voltage and the first node, and an inverter driving a word line with the power-supply voltage or a ground voltage in accordance with the voltage of the first node. When a corresponding word line is activated, the second node is set at the ground voltage while the first transistor is turned on. In a burn-in test, a burn-in control circuit forcibly turns off the second transistor in a local decoder corresponding to a word line to be activated.

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Tokyo, Japan

Hidemoto Tomita