Rohm Co., Ltd.

Other

National Institute of Advanced Industrial Science and Technology

Hidemi Takasu

Takashi Nakamura

Ken Nakahara

Yoshikazu Fujimori

Noriyuki Shimoji

Hiromitsu Kimura

Takahiro Hanyu

Shigeru Niki

Paul Fons

Tetsuhiro Tanabe

Kakuya Iwata

Michitaka Kameyama

Hiroaki Ohta

Masahide Tanaka

Takanori Ozawa

Takuji Maekawa

Toshihisa Maeda

Tsuneo Fujikawa

A target is irradiated in a time-shared manner with a visible-light-range illumination light source and an infrared laser beam for Raman scattering, and a target image is formed with an image-capturing lens on a CIGS image sensor provided with a visible-light-range filter, a narrow-band infrared filter for Raman-scattered light measurement, and a near-band reference narrow-band infrared filter that does not let Raman-scattered light pass through. In a preliminary measurement, a plurality of normal sections are measured and averaged, and by using the same as a reference, an actual measurement of Raman scattering is performed. In displaying a visible-light image with the CIGS image sensor, superimposed display is performed to specify sections where Raman scattering is detected, and superimposed display positions are corrected in association with focusing and zooming. The displaying of the visible-light image is continued even during the detection of Raman scattering.

Cancer diagnostic device, diagnostic system, and diagnostic device

The semiconductor device includes a P-type group III-V nitride semiconductor layer, an N-type group III-V nitride semiconductor layer, and an electrode in contact with both of the P-type group III-V nitride semiconductor layer and the N-type group III-V nitride semiconductor layer. The electrode includes a first electrode portion made of a first conductive material, and a second electrode portion, made of a second conductive material different from the first conductive material, bonded to the first electrode portion. The first electrode portion is in contact with the P-type group III-V nitride semiconductor layer, and the second electrode portion is in contact with the N-type group III-V nitride semiconductor layer.

Semiconductor device employing group III-V nitride semiconductors and method for manufacturing the same

The MIS field-effect transistor includes: a substrate; a nitride semiconductor multilayer structure portion formed on the substrate, including a first group III-V nitride semiconductor layer of a first conductivity type, a second group III-V nitride semiconductor layer of a second conductivity type stacked thereon and a third group III-V nitride semiconductor layer of the first conductivity type stacked thereon; a gate insulating film formed on a wall surface formed over the first, second and third group III-V nitride semiconductor layers to extend over these first, second and third group III-V nitride semiconductor layers; a gate electrode made of a conductive material formed as being opposed to the second group III-V nitride semiconductor layer via the gate insulating film; a drawn portion electrically connected to the first group III-V nitride semiconductor layer and drawn from the nitride semiconductor multilayer structure portion in a direction parallel to the substrate; a drain electrode formed in contact with the drawn portion; and a source electrode electrically connected to the third group III-V nitride semiconductor layer.

MIS field effect transistor and method for manufacturing the same

A light emitting device includes a silicon substrate (), a silicon nitride film () formed on the surface of the silicon substrate (), at least an n-type layer (), () and a p-type layer (), () which are formed on the silicon nitride film () and also which are made of a ZnO based compound semiconductor, and a semiconductor layer lamination () in which layers are laminated to form a light emitting layer. Preferably this silicon nitride film () is formed by thermal treatment conducted in an atmosphere containing nitrogen such as an ammonium gas. Also, in another embodiment, a light emitting device is formed by growing a ZnO based compound semiconductor layer on a main face of a sapphire substrate, the main face being perpendicular to the C-face thereof. As a result, it is possible to obtain a device using a ZnO based compound with high properties such as an LED very excellent in crystallinity and having a high light emitting efficiency.

ZnO based compound semiconductor light emitting device and method for manufacturing the same

A logical calculation circuit capable of storing data, and performing logical calculations with high reliability and high speeds are provided. The residual polarized state s' of a load ferroelectric capacitor Cs&#x2032; is actively changed so that the residual polarized state s&#x2032; of a load ferroelectric capacitor Cs&#x2032; is opposite to the residual polarized state s of a storage ferroelectric capacitor Cs. In the case a reference potential is made c=0 in the calculation operation, even if the second data to be calculated x=1 is given to the storage ferroelectric capacitor Cs in the residual polarized state s (the first data to be calculated)=0, the ferroelectric capacitor Cs does not reverse in polarity. Even with combinations other than s=0 and x=1, the ferroelectric capacitor Cs does not reverse in polarity. Difference is great between a potential VA=VA(0) occurring at a coupling node when x=1 is given to the ferroelectric capacitor Cs of s=0 and a potential VA=VA(1) occurring at the coupling node when x=1 is given to the ferroelectric capacitor Cs of s=1.

Logical calculation circuit, logical calculation device, and logical calculation method

To provide a logical operation circuit which can perform a logical operation using a ferroelectric capacitor and a logical operation method. A logical operation circuithas a ferroelectric capacitors CF and a transistor MP. The ferroelectric capacitor CF can retain a polarization state P(y=1) or P(y=0) corresponding to first operation target data y. In an operation process, a first terminalof the ferroelectric capacitoris precharged to a source potential Vdd, and a potential corresponding to second operation target data x, that is, a ground potential GND (x=1) or the source potential Vdd (x=0), is given to a second terminalof the ferroelectric capacitor via a bit line BL. When the threshold voltage Vth of the transistor MP is set properly, the transistor MP becomes on or off (on, on, on, off) depending on the combination of x and y (0-0, 0-1, 1-0, 1-1).

Logical operation circuit and logical operation method

To provide a logical operation circuit and a logical operation method which can perform a logical operation using a ferroelectric capacitor. A logical operation circuithas ferroelectric capacitors CFand CFand a transistor MP. The ferroelectric capacitor CFcan retain a polarization state Pcorresponding to a logical operator. In an operation and storage process, a source potential Vdd corresponding to first operation target data y=1 and a ground potential GND corresponding to second operation target data y=0 are given to a first terminaland a second terminal, respectively, of the ferroelectric capacitor CF. The polarization state of the ferroelectric capacitor CFis thereby shifted to P. A residual polarization state corresponding to the polarization state Pis P. The residual polarization state changes (P, P, Por P) depending on the combination of yand y(0-0, 0-1, 1-0 and 1-1). In a reading process after that, an output corresponding to the residual polarization state is obtained via the transistor MP.

A process for fabricating a semiconductor device having a buried layer comprises the steps of implanting an impurity ion into where the buried layer to be formed in a substrate, providing the substrate inside a reactor furnace, preparing a nonoxidizing atmosphere inside of the reactor furnace, annealing the substrate to activate and diffuse the implanted impurity ion region while increasing inside temperature of the reactor furnace up to a first temperature, and shifting the inside temperature of the reactor furnace from the first temperature to a second temperature in which a epitaxial crystal starts to grow and introducing a epitaxial growth gas into the reactor furnace to grow an epitaxial layer on a surface of the substrate.

Process for fabricating semiconductor device

A semiconductor nonvolatile memory cell comprised of a p-type silicon well, an ndrainand an nsource, the source and the drain regions defining an channel region. On top of the wellthere are laminated a thin silicon dioxide filmserved as a gate oxide, a polysilicon layerand a SrTiOlayercomprised of a high dielectric substance, in respective order. Further on top of these layers, there is formed a polysilicon layerserved as gate electrode. By using the memory cell and appropriate select transistors, a semiconductor nonvolatile memory device is constructed.

Semiconductor nonvolatile memory with low programming voltage

The present invention provides a practical device which can hold data even if the power is shut OFF, and more particularly to a data holding device which has a high detection margin at data restoration and has high reliability. The data holding device comprises a data latch circuit and a composite capacitor . The data holding device can store the data in the ferroelectric capacitors and in a non-volatile way. A voltage the same as the power supply voltage VDD is applied across the composite capacitor where the ferroelectric capacitors and are connected in a series, and data is restored by detecting the voltage which is generated at the connection node at this time. As a result, the detection margin can be dramatically increased.

Data holding device and electronic circuit having data holding device

A light emitting device includes a silicon substrate ( ), a silicon nitride film ( ) formed on the surface of the silicon substrate ( ), at least an n-type layer ( ), ( ) and a p-type layer ( ), ( ) which are formed on the silicon nitride film ( ) and also which are made of a ZnO based compound semiconductor, and a semiconductor layer lamination ( ) in which layers are laminated to form a light emitting layer. Preferably this silicon nitride film ( ) is formed by thermal treatment conducted in an atmosphere containing nitrogen such as an ammonium gas. Also, in another embodiment, a light emitting device is formed by growing a ZnO based compound semiconductor layer on a main face of a sapphire substrate, the main face being perpendicular to the C-face thereof. As a result, it is possible to obtain a device using a ZnO based compound with high properties such as an LED very excellent in crystallinity and having a high light emitting efficiency.

ZnO compound semiconductor light emitting element

A method of manufacturing a ferroelectric memory device which has a gate structure constituted by a ferroelectric layer and a conductor layer stacked on a semiconductor substrate. The method includes steps of forming the gate structure section by patterning the ferroelectric layer and the conductor layer through etching using a common mask layer, introducing impurities into the semiconductor substrate in a self-aligning manner with respect to the gate structure section, and annealing simultaneously both of the ferroelectric layer and the impurities introduced into the conductor substrate to crystallize the ferroelectric layer and at the same time activate the impurities thereby to form a pair of impurity diffused layers.

Method of manufacturing ferroelectric memory device

It is an object of the present invention to provide a sequential circuit having nonvolatile characteristics capable of holding data therein even when the power supply is shut-off. An inverter circuit INV,is formed by replacing a pair of transistors consisting the conventional CMOS inverters with transistors NT and PT both having an MFMIS structure. A polarization state corresponding to an ON state is held in a ferroelectric layer,of the transistor NT even when the power supply thereof is shut off, and another polarization state corresponding to an OFF state is held in a ferroelectric layer,of the transistor PT. The transistors NT and PT are turned into ON and OFF state respectively according to the polarization states held in their ferroelectric layers,when the power supply is turned ON again. In this way, the inverter circuit INV,recovers its state to the state right before the shut-off by turning the power supply into the ON state again.

Sequential circuits using ferroelectrics and semiconductor devices using the same

One NPN or PNP transistor is formed on a Si single crystal island having a crystal orientation which is the same as that of a Si substrate and formed into an island shape through an insulation and separation layer on the Si substrate so as to form a semiconductor apparatus which has no parasitic junctions.

Growing community of inventors

Kyoto, Japan

Hidemi Takasu