Kabushiki Kaisha Toshiba

Hidemasa Zama

Kimiyoshi Usami

Toshiyuki Furusawa

Masayuki Koizumi

Masahiro Kanazawa

Naoyuki Kawabe

Daisuke Sonoda

Yukiko Ito

A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Semiconductor integrated circuit with reduced leakage current

Semiconductor integrated circuit, logic operation circuit, and flip flop

Semiconductor circuit having a combination circuit being switched between an active and inactive state

An automatic circuit generation methods and apparatus ( ) provide a desired circuit performance by reducing a leakage current during both a standby state and an active state, where cells having only High-Vth and Mt cells having both High-Vth transistors and Low-Vth translators are optimally mixed in a logical circuit. It is thereby possible to suppress efficiently the leakage current, in a design stage, generated according to miniaturization of LSI layout design and also lowering a supply voltage to the LSI.

Automatic circuit generation apparatus and method, and computer program product for executing the method

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Kawasaki, Japan

Hidemasa Zama