Kabushiki Kaisha Toshiba

Other

Hideko Odaira

Tomoharu Tanaka

Yoshiyuki Tanaka

Yoshihisa Iwata

Yasuo Itoh

Masaki Momodomi

Riichiro Shirota

Seiichi Aritome

Hideo Kato

Masamichi Asano

Yutaka Okamoto

Hiroto Nakai

Kaoru Tokushige

Takashi Mori

Hiroshi Nakamura

Fujio Masuoka

Tetsuo Endoh

Ryouhei Kirisawa

Ryozo Nakayama

The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Non-volatile semiconductor memory device and memory system using the same

The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

A method for controlling programming of an electrically erasable and programmable nonvolatile memory having a plurality of memory cells, row and column decoders, an address buffer, and a bit line controller including a sense/latch circuit and a data I/O buffer, including supplying address signals to the address buffer to define at least one selected memory cell in the plurality of memory cells; supplying to the bit line controller programming data which corresponds to write data to be written in the selected memory cell; latching the programming data in the sense/latch circuit; writing the write data into the selected memory cell; reading the written data of the selected memory cell and verifying whether or not the data is successfully written; performing a logic operation with respect to the read data and the programming data latched in the sense/latch circuit to determine if the written memory cell is insufficiently written or successfully written; and if an insufficiently written memory cell is found, maintaining the programming data and rewriting the write data into the insufficiently written memory cell.

Electrically erasable and programmable nonvolatile semiconductor memory with automatic write-verify controller

A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense/latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier after being reset.

Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller

A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation if the write data. A program controller is provided for writing the data into a selected memory cell in the designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier once after it is reset.

Method for programming an electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller

Non-volatile semiconductor memory device with an improved verify voltage generator

A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto. A rewrite-data setting section is provided for performing a logic operation with respect to a read data from the selected cell and the write data being latched in the sense/latch circuit, and for updating automatically a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the actual write state as being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier once after it is reset.

Electrically erasable and programmable non-volatile semiconductor memory

A NAND-cell type EEPROM having an array of memory cells connected to bit lines. Each cell includes one transistor with floating and control gate electrodes. Electrons are tunneled to or from the floating gate to write data. A sense/latch circuit is connected to the bit lines for selectively performing sense and latch operations of the write data. A program controller is provided for writing and verifying the data into a selected memory cell. Data is rewritten if a resultant threshold voltage in the selected memory cell of the written data is insufficient. A rewrite-data setting section is provided for performing a logic operation with respect to data read from the selected cell and write data being latched into the sense/latch circuit, and for automatically updating a rewrite data being stored in the sense/latch circuit with respect to every bit line in accordance with the memory being verified. The sense/latch circuit includes a CMOS flip-flop circuit, which acts as a data-latch at the beginning of the verify operation, and serves as a sense amplifier after being reset.

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Machida, Japan

Hideko Odaira