Fujitsu Corporation

Anelva Corporation

Hideki Yoshizawa

Hideki Kato

Hiroki Iciki

Tatsushi Otsuka

Daiki Masumoto

Kazuo Asakawa

Katsuhito Fujimoto

Chikara Tsuchiya

Katsuya Ishikawa

Takashi Kawasaki

Yoshihide Sugiura

Hiromu Iwamoto

Toshiharu Matsuda

Hiroyuki Tsuzuki

Hideichi Endo

Yuji Nomura

Hiroshi Furukawa

Shiro Uriu

Tetsu Tanizawa

Miyoshi Saito

Shigeru Sasaki

Hisanori Fujisawa

Tetsuo Kawano

Toru Tsuruta

Ichiro Kasama

Mitsuharu Wakayoshi

Kazuaki Imafuku

Naoki Sasaki

Norichika Kumamoto

Ritsuko Tatematsu

Hideichi Endoh

An arithmetic-logic unit for performing an operation of a prescribed bit length in an execution stage of a processor includes a plurality of sub-arithmetic-logic units which perform in respectively different pipeline stages sub-operations created by decomposing the operation of the prescribed bit length in a bit length direction, and a plurality of pipeline registers provided so as to separate the pipeline stages from each other, wherein each of the pipeline registers operates in such a manner as to be switchable between two operation modes, a flip-flop mode in which an output value is updated in synchronism with an input trigger and a transparent mode in which an input value is directly output.

Processor having ALU with dynamically transparent pipeline stages

A disclosed signal transmitting method includes the steps of a) categorizing plural digital signals, obtained by performing A/D conversion on plural analog signals consecutively arranged in a time direction, into plural signal groups in an order starting from lower bits of the plural digital signals, b) performing code spreading on the plural digital signals by using a different spread frequency for each signal group and using different spread codes for each bit, c) multiplexing the spread digital signals, and d) transmitting the multiplexed plural digital signals.

Signal transmitting method, transmitting apparatus, and receiving apparatus used for the signal transmitting method

A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Array processor having reconfigurable data transfer capabilities

In a method of manufacturing a liquid crystal panel including a panel assembly, a nozzle mechanism is located at a vicinity of a liquid crystal filling port of the panel assembly with leaving a space between an intake of the nozzle mechanism and the liquid crystal filling port. The nozzle mechanism sucks surrounding gaseous to generate negative pressure and a continuous gaseous flow around the liquid crystal filling port. The negative pressure discharges an excess of liquid crystal filled in the panel assembly while the continuous gaseous flow blows the discharged liquid crystal. The blown liquid crystal is sucked into the intake of the panel assembly. Thus, a gap of the panel assembly is adjusted within a proper range in a short time.

Method of manufacturing liquid crystal panel and gap adjusting apparatus therefor

A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus. Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units. The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor. If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated.

Signal processing device accessible as memory

An information processing apparatus includes a dedicated graphic hardware part dedicated to execution of a specific process function under a pipeline process scheme, and a microprogram execution part executing a process using a microprogram. When three-dimensional graphic information is processed, a process for determining endpoints is executed by the microprogram execution part, and an interpolation process started from an endpoint is executed by the dedicated graphic hardware part for each endpoint process. While the dedicated graphic hardware part is executing the interpolation process, the microprogram execution part is operated in parallel so as to execute the endpoint process for a next endpoint.

Information processing apparatus and method for processing three-dimensional graphics using a second information processing unit for processing processed-related information

A prediction block address is generated from a current block address in accordance with a rule specified by a prediction mode signal. One of two cache memory banks is allocated as a current bank and the other is allocated as a prediction bank. When the current block address is stored in the prediction bank, the allocation of the current and prediction banks is reversed. When the prediction block address is not stored in the prediction bank, a data block specified by the prediction block address is block-read into the prediction bank.

Cache-memory system having multidimensional cache

Graphic data having a two-dimensional spread is divided into data blocks having a two-dimensional spread, for example, data blocks of 8.times.8 pixels, and with these data blocks as units, cache control is performed. A tag memory for making a decision as to the occurrence of a cache hit, stores therein a tag and a valid flag as well as a bank address in a cache memory at which the data block in question is stored. As a result, the relationship between each bank of the cache memory and the address in the tag memory is not fixed, which ensures efficient use of the cache memory even in situations where accesses concentrate in one particular memory area.

Cache-memory system having multidimensional spread cache

A parallel computer includes a sequence of adjacent nodes, with each node including at least first and second processing elements and each processing element including a memory. The nodes are sequentially added or replaced in a node order and the processing elements are sequentially connected to form a single ring data path. First matrix data elements are sequentially assigned to adjacent processing elements along the single ring data path and second matrix data element groups are sequentially assigned to processing elements in the node order. The first matrix data elements are then accumulated with the second matrix data element groups as the first matrix data elements are rotated along the single ring data path. Accordingly, accumulation results are maintained within the memories of the lowest order nodes such that the nodes may added or replaced without relocation of data.

Parallel computer

A parallel data processing system uses a parallel learning method capable of having sufficient parallelness to shorten learning time and has plural data processing units, each connected to a data transfer unit and having a unit for holding execution parameters as are required for data processing, a unit for holding partial sample data which comprises at least part of the full sample data necessary for the required data processing, an adjustment value calculation unit which calculates, from partial sample data stored in the unit for holding partial sample data and from the execution parameters held in the execution parameter holding unit, adjustment amounts related to the execution parameters with regard to the partial sample data and, further, an accumulator which, when calculating the overall total of the execution parameter adjustment amounts with regard to the full sample data, accumulates the adjustment amounts related to the execution parameters with regard to the partial sample data at the data processing units and the adjustment amounts related to the execution parameters with regard to the partial sample data at other data processing units by the data transfer unit.

Parallel data processing system

A parallel data processing system comprises a plurality of data processing units each having at least one input and storing data of a matrix and a plurality of trays each having a first input and an output and for storing data of a vector, each of all or part of said trays having a second output connected to said first input of a respective one of said data processing units, and said trays being connected in cascade to form a shift register for performing data transfer between corresponding ones of the trays and the data processing units and data processing in the data processing units synchronously, thereby performing an operation of a matrix vector product or a neuron computer operation on analog signals.

Ring systolic array system for synchronously performing matrix/neuron

A parallel data processing system processes data by synchronously operating a plurality of data processing units (processor elements). It aims at reducing the overhead caused by the data transmission in a system, performing a matrix operation and a neurocomputer operation by making the best of its parallel processing method, and at using excess units for another operation when the number of units required for an operation is smaller than the number of the existing units. The parallel data processing system comprises a plurality of data processing units; a plurality of trays which store and transmit data, each connected to a data processing unit; a tray connection switching unit for changing the connection state of the data transmission path between trays, dividing data processing units into a plurality of groups, and performing an independent operation on each group; and a clock generator for synchronously operating a data transmission between trays and a data process in a data processing unit. Thus, the data are transmitted while the data are processed, so the data transmission time can be actually counted as zero.

Parallel data processing system which efficiently performs matrix and

A parallel data processing system performs a data processing by using a plurality of data processing units, namely, processor elements, synchronously. The parallel data processing system comprises a plurality of data processing units, a plurality of trays, and a clock generator. The plurality of trays are connected to respective data processing units and have a function of storing a plurality of data and a function of transmitting the data. The clock generator is producing a clock so that the data transfer between the trays and between the trays and the data processing units, and the data processing in the data processing unit is executed synchronously. Data are transferred between trays during the period in which they are processed, thus substantially eliminating the data transmission time. Furthermore, the interim result of the operation is stored in the tray and thus when the later operation needs the interim result, the interim result stored in the tray is efficiently used without the need to access the memory provided in the data processing apparatus.

Parallel data processing system using a plurality of processing elements

An asynchronous control system for a neuro computer, includes an inter-connected type neural network composed of a plurality of neurons for multiplying a plurality of input signals with corresponding weights, calculating a total sum-of-products of the input signals and weight, thereby providing the sum-of product signals, and converting the sum-of-product signal using a non-linear function. A weight memory is provided for storing data of the weights for said neurons, and a controller is provided for generating a control pattern which controls the neural network. A selector randomly selects one of the neurons which performs signal processing during one processing cycle.

Asynchronous control system for a neuro computer

A floating-point arithmetic system, which allows arithmetic operations, including at least addition and subtraction, to be performed for floating-point data. The system includes multiple-input addition and subtraction devices for executing adding and subtracting calculations of at least three floating-point data. Preferably, the multiple-input addition and subtraction devices includes a multiple-input device which enables at least three floating-point data to be input, a shift-amount determining device having a look up table which compares the respective exponents in parallel, selects the maximum exponent and determines the amount of shift in the respective mantissas; and a mantissa shifting devices, e.g., at least one multiplexer, which shifts the respective mantissas in accordance with the amount of shift and makes an adjustment of digit positions of the mantissas. The system also includes at least one multiple-input adder-subtractor which executes addition and subtraction for the mantissas output from the mantissa shifting device, and a normalization circuit which normalizes a result obtained by the multiple-input adder-subtractor.

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Kawasaki, Japan

Hideki Yoshizawa