Kabushiki Kaisha Toshiba

Sony Computer Entertainment Inc.

Hideki Yasukawa

Atsushi Kunimatsu

Yukio Watanabe

Kiyoji Ueno

Takayuki Kamei

Takanao Amatsubo

Nobuo Sasaki

Yuji Suzuki

Harutaka Goto

Systems and methods for accelerators which may execute a program in conjunction with a PC are disclosed. In one embodiment, an accelerator includes a plurality of calculation units, each calculation unit operable to execute the program in parallel, an operation control unit configured to control an operation capability or a processing capability of at least one of the plurality of calculation units, and a control unit configured to determine a corresponding operation capability or processing capability for the plurality of calculation units based on load information on the program to be executed and control the operation control unit accordingly.

Accelerator load balancing with dynamic frequency and voltage reduction

A secondary texture cache is used commonly by a plurality of texture units, and stores part of texture data in a main memory. A cache controlling CPU controls a refill operation from the main memory to the secondary texture cache in accordance with cache misses of the plurality of texture units, so as to suppress occurrence of thrashing in the secondary texture cache. The cache controlling CPU suppresses occurrence of the refill operation when the plurality of operating units access an identical memory address with a predetermined time difference.

Information processing apparatus with a cache memory and information processing method

The present invention provides an image processing unit, an image processing system, and an image processing method capable of achieving a higher speed and a higher efficiency in a rendering and implementing a low cost of the system. The image processing unit according to the present invention comprises a main storing portion for storing information of three-dimensional objects, a plurality of calculating portions for processing images based on three-dimensional object information which are read from the main storing portion, and a hierarchical storing portion having a plurality of hierarchies and connected between the main storing portion and the plurality of calculating portions to store a part of information at a lower level into a higher level sequentially, wherein image processing by the plurality of calculating portions are performed in parallel.

Image processing unit, image processing system using the same, and image processing method

Method of the apparatus for transferring data between circuits

Growing community of inventors

Kanagawa, Japan

Hideki Yasukawa