Mitsubishi Denki Kabushiki Kaisha

Hideki Taniguchi

Katsushi Asahina

Ichiro Tomioka

Masatomi Okabe

Kunihiko Sanada

Yoichi Goi

Naoto Ueda

Hideo Kameda

Masahiro Suzuki

In a semiconductor integrated circuit, an input-output circuit includes a flip-flop circuit (a front stage of an output circuit) between an input circuit unit and a tri-state output circuit unit (a final stage of an output circuit). This input-output circuit converts the level of the signal supplied from an internal circuit, which is operated by a first power source system, which provides a first supply potential and a grounding potential, of an LSI. After elapse of a certain time delay, the input-output circuit outputs a level converted signal to a device, which is operated by a second power source system, providing a second supply potential and a grounding potential, outside of the LSI.

Semiconductor integrated circuit

To prevent a through current from flowing through a pair of MOS transistors of a final stage of a push-pull buffer circuit, a reset circuit is provided which receives signals individually from two inverter gate groups of a control system and an output system disposed at the stage preceding the push-pull buffer circuit, delays the input signals, and makes a logical decision on them. Even when an input/output circuit formed by two power supply systems becomes unstable at the time of power ON-OFF operation and the signal output from a signal level converter circuit yields logic that causes a through current flow into the final stage, the reset circuit forcedly cancels this logic by feedback.

Output buffer circuit

A semiconductor device includes a buffer region having buffers and disposed along a side of a semiconductor chip; a pad region having pads corresponding to the buffers and disposed outside the buffer region on the semiconductor chip; signal lines connecting the buffers to corresponding pads; and power supply lines and ground lines connected to extra pads, either of the power supply lines or the ground lines being partially superimposed on part of and separated from the signal lines by insulating layers.

Semiconductor device

An input/output circuit in which, one of the two output signals from a signal level converting circuit is inputted into one input terminal of a NAND gate and into one input terminal of a NOR gate, while the other signal is inputted into the other input terminal of the NOR gate and also to the other input terminal of the NAND gate through an inverter. An output signal from the NAND gate and NOR gate is inputted into the gate of a PMOS transistor and into a gate of a NMOS transistor, which makes it possible to prevent the PMOS transistor and NMOS transistor from concurrently being ON and also prevents a through current from flowing therethrough.

Input/output circuit

An output buffer circuit is provided which comprises a level conversion circuit having a first conversion circuit for converting a control signal and an output signal to 'H' and 'L' signals in a first source system and a second conversion circuit for converting these into 'H' and 'L' signals in a second source system, a tristate control type input/output control circuit for computing the 'H' and 'L' signals outputted from the second conversion circuit in the second source system, and a push-pull circuit having MOS transistors Q13a and Q14, which is activated in the second source system in response to the 'H' and 'L' signals so as to select a tristate and output it as an input/output signal.

There are provided an output buffer circuit and an input/output buffer circuit each including pre-driver circuit and main driver circuit divided to a plurality of stages and a delay circuit and enabling operations of the main driver circuit successively with a delay circuit in the pre-driver circuit.

An output buffer circuit for controlling operation of an input and output terminal utilizing a pair of MOS Transistors respectively formed in first and second wells in a substrate. The input and output terminal is connected commonly to the source of the first MOS transistor, to the drain of the second MOS transistor and to the well of the first MOS transistor in order to hold the well at the same potential as the input and output terminal. Also included is a first potential point applying a first potential to the drain of the first MOS transistor and a second potential apply commonly to the source and the well electrode of the second MOS transistor. The resulting structure controls the operating state of the input and output terminal in a manner which allows for an enhanced output potential.

A detecting penetration current causing logic part (12a) gives, when the logic is H level at both nodes (N15, N24), the logical product thereof H to a condition adding part (12b) as an activated detection signal. In the condition adding part (12b), it is confirmed that the activation of the detection signal is longer than a specified time, by a delay circuit (G21) and NAND gate (G22). Consequently, logic H is given to a forced logic presenting part (12c). In the forced logic presenting part (12c), NMOS transistors (Q13, Q14) are turned on, and logic L is given by force to both nodes (N15, N24) to get out of a state where a current would flow.

A master-slice semiconductor integrated circuit device includes a substrate for an input/output circuit section, which is segmented into a plurality of segments during a master processing step. In a slice processing step, slice cells are formed, using different substrate segments. Input/output circuits are formed by respective slice cells so that desired different supply voltages can be applied to input/output circuits on different substrate segments.

Multi-voltage-lever master-slice integrated circuit

A plurality of different power source potentials are optionally selected in a semiconductor integrated circuit. First and second semiconductor segments (3) and (4) are both in the form of a number of rows which are separated from each other by spacings (14). Power source wires (6) and (7) for supplying potentials (V1) and (V2) are disposed above the second semiconductor regions (4). Cells are formed in different wells, and therefore, it is possible that different cells receive different power source potentials. Contacts (61) or (71) are made to the second semiconductor segments (4) so that the second semiconductor segments (4) are connected to the power source wire (6) or (7). Selection of and connection to one of the wires are attained in a slicing process.

Growing community of inventors

Tokyo, Japan

Hideki Taniguchi