Kabushiki Kaisha Toshiba

Nippon Steel Corporation

Mitsubishi Jidosha Kogyo Kabushiki Kaisha

Tokyo Electron Limited

Metawater Co., Ltd.

Nec Corporation

Mitsubishi Jidosha Engineering Kabushiki Kaisha

Hideki Takeuchi

Masaaki Yamada

Mutsunori Igarashi

Masami Murakata

Takashi Ishioka

Reiko Nojima

Mototaka Kuribayashi

Chishio Koshimizu

Akira Koshiishi

Shigeyuki Hayakawa

Jun Ooyabu

Takuya Fujimoto

Kiyotaka Sugiura

Hirohiko Izumi

Hiroyuki Oyachi

Junichi Tsujimoto

Tomoaki Yabe

Yoshiharu Hirata

Kimiaki Tanaka

Koichiro Kawamura

Yusuke Okada

Sadamitsu Shiode

Satoru Mima

Hideo Okada

Akihiro Matsui

Yasuhiro Tonooka

Kentaro Kuroiwa

A method of removing soluble manganese includes: a mixing step of mixing water for treatment, activated carbon micropowder having an average particle size of not less than 0.1 &#x3bc;m and not more than 10 &#x3bc;m, and an oxidizing agent to obtain a water/activated carbon mixture; and a membrane filtration step of membrane filtering the water/activated carbon mixture to obtain treated water.

Method of removing soluble manganese

A vehicle body structure is provided to avoid the damage to a battery pack due to invasion of an electric device in a side impact crash. The vehicle body structure includes a battery pack on its inner side in a vehicle width direction, and an electric device on its outer side. A No1 seat cross memberis provided along in the vehicle width direction of the floor panel. The No1 seat cross memberis provided with a weak portionin a position in the vehicle width direction corresponding to between the battery packand an electric hot-water heateras the electric device.

Vehicle body structure

A battery box includes a flange, a side wall and a bottom wall. The flange is connected to an inner peripheral edge of an installation hole formed in a floor panel of a vehicle. The side wall gently continues with the flange, and is extended downward. The bottom wall, has a periphery gently continuing with the side wall, and is formed with at least one open hole in a center of the bottom wall. Seat portions are projected upper than the bottom wall. At least one seat portion is disposed at each both sides of the open hole. A bottom cover closes the open hole. A corner portion gently continues with the side wall and the bottom wall forming curved surface. A center of curvature of the curved surface is set inside a corner of a battery to be placed on the seat portions.

Battery box

A front part body structure of a vehicle, includes: an upper frame which is extended in a longitudinal direction of the vehicle, one end of which is joined to a front pillar, and which includes an inner panel and an outer panel, the outer panel that is divided in a dividing part in the longitudinal direction of the vehicle; and a first partition wall which is provided between the inner panel and the outer panel, one end of which is joined to the inner panel, and the other end of which is fastened and fixed to the dividing part of the outer panel by means of a fastening member.

Front part body structure of vehicle

The present invention provides an upward-flow manganese contact column for feeding raw water to a manganese catalyst-packed layer through a plurality of dispersion nozzles provided at the upper surface of a chamber by forming the chamber for allowing raw water to flow in at the bottom of a column body into which a granular manganese catalyst is packed. Each dispersion nozzle has an umbrella portion above a perpendicular nozzle body, and the umbrella portion is configured so that the lower end of the umbrella portion is elongated below the upper end of the nozzle body. Raw water is supplied to the entire manganese catalyst-packed layer from the lower end of the umbrella portion of each dispersion nozzle. It is capable, of exhibiting stable treatment ability for a long time by suppressing particles of the manganese catalyst from being worn by collisions of the particles.

Upward-flow manganese contact column

A semiconductor integrated circuit device comprises a semiconductor memory circuit including a memory cell array in which normal cells are integrated and a fuse circuit in which fuse cells that store operation information of the semiconductor memory circuit are integrated. The fuse cell is of a 2-transistor type memory cell which comprises a cell transistor having a charge storage layer and a selection transistor which selects the cell transistor.

Semiconductor integrated circuit device

The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive. Moreover, a communication circuit for setting the number of data buses to be newly added to be less than two times a transmission on data, then encoding the data to be sent so as to make the numbers of '0' and '1' in the data to be sent through the data buses equal to each other and accordingly reducing the increase of the number of the data buses to a minimum and thereby suppressing the common phase power supply noise is provided. A communication apparatus comprising the communication circuit is also provided. Furthermore, the bypass capacitor C for noise suppression circuit is formed in an empty space in a ASIC. A polysilicon layer constituting one electrode of the bypass capacitor is formed in the substrate contact region formed between basic cells regularly arranged, each including a plurality of nMOS and pMOS transistors. This bypass capacitor C is connected between the high and the low level power supply lines to reduce the current running through the power supply line to suppress the EMI noise.

Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same

A semiconductor memory device including: a first memory cell array including a plurality of memory cells, a first switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the first memory cell array, a latch circuit for latching the data transferred from the first switch circuit, a first write selector circuit for transferring the data transferred from the latch circuit, a first bit line connected to at least one of the plurality of memory cells and receiving the data transferred from the first write selector circuit, a second memory cell array including a plurality of memory cells that are different from the plurality of memory cells arranged in the first memory cell array, a second switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the second memory cell array, a second write selector circuit connected to the second switch circuit and transferring the data transferred from the second switch circuit, and a second bit line connected to at least one of the plurality of memory cells arranged in the second memory cell array.

Semiconductor memory device having first and second memory cell arrays and a program method thereof

A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.

A plasma processing method comprises the steps of supplying a low-frequency bias to a first electrode carrying a substrate, and supplying a high-frequency power to a second electrode facing the first electrode, wherein the low-frequency bias is supplied to the first electrode in advance of starting plasma by the energy of the high-frequency power, with an electric power sufficient to form an ion-sheath on the surface of the substrate.

Plasma processing method and apparatus for eliminating damages in a plasma process of a substrate

The method of the present invention comprises the steps of: provisionally updating a resource through a first transaction program and locking the resource; determining if a second transaction program generates a request to update the resource which has been locked because of the provisional update through the first transaction program; making the second transaction program exclusively wait and reproducing a third transaction program having an internal status identical to that of the second transaction program when the second transaction program generates the update request; providing a virtual resource having an original status before the provisional update through the first transaction program; provisionally updating the virtual resource through the third transaction program without exclusive wait; and rolling back and closing the exclusively waiting second transaction program and executing commit in the reproduced third transaction program when rollback of the first transaction program is executed due to an abnormal situation detected in the first transaction program.

Method and apparatus for executing transaction programs in parallel

In a semiconductor storage device, an access transistor, which has a gate electrode and a pair of impurity diffusion layers, is formed at a device activation region defined by a device isolation structure of a semiconductor substrate. A first insulating film, which has a first contact hole for exposing a portion of the surface of one of the pair of impurity diffusion layers, is formed over the access transistor. A protective film, which has a second contact hole formed on the first contact hole, is formed on the first insulating film. A second insulating film is formed on the side wall faces of the first and second contact holes. A memory capacitor has a lower electrode and an upper part electrode which are opposed each other and are capacitive-coupled through a dielectric film. The lower electrode is filled inside the first and second contact holes to be formed in an island-like shape on the first insulating film through the protective film so as to be electrically connected with the one of the pair of impurity diffusion layers. Each of the first and second contact holes has a diameter which is made smaller by an existence of the second insulating film than a minimum dimension determined by an exposure limit in a photolithography.

Method of fabricating semiconductor storage device having a capacitor

Noise suppression circuit, ASIC, navigation apparatus communication circuit, and communication apparatus having the same

A plasma processing method includes supplying a low-frequency bias to a first electrode carrying a substrate, and supplying a high-frequency power to a second electrode facing the first electrode, wherein the low-frequency bias is supplied to the first electrode in advance of staring plasma by the energy of the high-frequency power, with an electric power sufficient to form an ion-sheath on a surface of the substrate. A plasma processing apparatus is also provided.

Growing community of inventors

Tokyo, Japan

Hideki Takeuchi