Fujitsu Corporation

Fujitsu Component Limited

Hideki Takauchi

Hirotaka Tamura

Kohtaroh Gotoh

Takashi Shiraishi

Osamu Daikuhara

Yoshiyasu Nakashima

Yu Yonezawa

Tsz-Shing Cheung

Masaki Aoki

Takashi Eshita

Shinichiro Matsuo

Hideki Ishida

Tomokazu Higuchi

Yuko Ohse

Yoshie Kanamori

An optical receiver includes a light receiving element array that includes a plurality of light receiving elements, a plurality of amplifiers that amplify respective currents obtained by the plurality of light receiving elements, a plurality of anode lines arranged in a region between the light receiving element array and the plurality of amplifiers, the plurality of anode lines coupling respective anodes of the plurality of light receiving elements to the plurality of amplifiers, respectively, and a cathode line disposed in a region different from the region between the light receiving element array and the plurality of amplifiers, the cathode line coupling respective cathodes of the plurality of light receiving elements to a bias power supply and a bypass capacitor.

Optical receiver

A mounting structure for a semiconductor element is disclosed. The semiconductor element is bonded to a die pad through an adhesive film, which is formed by applying a predetermined amount of a paste adhesive onto the surface of the die pad and placing the semiconductor element on the die pad so as to press and spread the adhesive between the lower surface of the semiconductor element and the die pad. A wire extends between the semiconductor element and a terminal pad disposed around the die pad. The die pad includes plural grooves in the surface thereof. Each of the grooves extends from the center of the die pad toward a peripheral edge of the die pad and ends at the inner side of the peripheral edge of the die pad.

Mounting structure for semiconductor element

A differential amplifier circuit has a latch unit and a differential input portion. A minute current is kept to flow through the differential input portion. Therefore, the differential amplifier circuit can accurately amplify even a signal high in speed and small in amplitude.

Differential amplifier circuit capable of accurately amplifying even high-speeded signal of small amplitude

A latch-type level converter has a signal-input transistor, a latch, and a clock-input transistor. The signal-input transistor, which is a high-voltage transistor, receives an input signal, and the latch holds data of the input signal received by the signal-input transistor. The clock-input transistor controls the operation in accordance with a clock. According to the latch-type level converter, not only can low-amplitude signals be accurately amplified, but also input signals having a common-mode voltage higher than the supply voltage can be received.

Latch-type level converter and receiver circuit accurately amplifying low-amplitude signals and receiving common-mode input signals higher than a supply voltage

A multiplexer circuit, converting parallel data into serial data and synchronized with a clock signal, has a plurality of multiplexer cells that receive the parallel data. Each of the multiplexer cells has a first load, a plurality of first conductivity type transistors, and a level-changing circuit. The first conductivity type transistors are connected in series between a first power source line and a second power source line, and the level-changing circuit changes a connection node of adjacent first conductivity type transistors to a level of the first power source line.

Multiplexer circuit for converting parallel data into serial data at high speed and synchronized with a clock signal

An output circuit has a data control circuit, a variable resistance circuit, a common-mode voltage detection circuit, an adjusting circuit. The data control circuit controls data included in an output signal according to an input signal, the variable resistance circuit is connected in series with the data control circuit between a first power supply line and a second power supply line. Further, the common-mode voltage detection circuit detects a common-mode voltage of the output signal, and the adjusting circuit adjusts a resistance of the variable resistance circuit according to an output of the common-mode voltage detection circuit. The common-mode voltage of the output signal is adjusted to equal an optional voltage, and an amplitude of the output signal is adjustable.

Output circuit capable of transmitting signal with optimal amplitude and optimal common-mode voltage at receiver circuit

A driver circuit transmits a signal to a receiver circuit through a signal transmission line. The driver circuit has an output driver, a front driver, and a level adjuster. The front driver drives the output driver, and the level adjuster adjusts the output level of the front driver. The output driver generates a signal whose level is variable in response to an output level of the front driver.

Timing signal generator for correctly transmitting a signal at high speed without waveform distortion

Method of an apparatus for correctly transmitting signals at high speed without waveform distortion

A ferroelectric memory capable of writing data at a small operation voltage has an insulated-gate field effect transistor, a ferroelectric film, and a pair of capacitor electrodes formed on the ferroelectric film and facing each other, one of the pair of capacitor electrodes being electrically connected to the insulated gate. A ferroelectric memory device with a simple structure has an insulated-gate field effect transistor including a source, a drain, and an insulated gate, and a ferroelectric capacitor connected between the drain and the insulated gate.

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Kawasaki, Japan

Hideki Takauchi