Nec Corporation

Safie Inc.

Dsm IP Assets B.v.

Jsr Corporation

Hideki Sugimoto

Yusuke Shimada

Hironori Sakamoto

Longshen Yang

Masanobu Sugimoto

A portable imaging device is configured to: obtain video data through shooting; perform a first digital image processing on the video data; and stop the first digital image processing when performing a second digital image processing on the video data while the first digital image processing is being performed. The second digital image processing is different from the first digital image processing.

Portable imaging device

A data processor has an internal data bus and an instruction fetch bus provided separately from each other. When a data-read operation mode is designated, data stored in an internal read only memory are read out onto both the internal data bus and the instruction fetch bus, and the data on these buses are then subject to an operation by an execution unit to check the coincidence therebetween, the comparison resultant signal being transferred to the outside.

Data processor having data bus and instruction fetch bus provided

A data processing apparatus executing in a pipelined manner a plurality of instruction including first and second instructions, the first instruction having first register address information and the second instruction having a second register address information, the data processing apparatus has a register file 110 including a plurality of registers, execution means 117, 118 for receiving and executing the first instruction to produce memory address information in a first pipeline cycle and for receiving and executing the second instruction to produce processed data, which is to be stored in the register file 110, in a second pipeline cycle succeeding to the first pipeline cycle, a memory circuit including a data memory 124 and an access control circuit reading out memory data, which is to be stored in the register file, from a memory area of the data memory 124 designated by the memory address information in the second pipeline cycle, and control means 133 for allowing the processed data to be stored in the register 110 file and preventing the memory data from being in the register file when the first register address information is coincident with the second register address information.

Pipeline data processing apparatus of reduced circuit scale

In a CPU comprising a CPU section and a BCU section, the processing speed of the CPU section is prevented from decreasing, the amount of power consumed by the CPU section is reduced, and the need of a wait control function in the CPU section is eliminated. A clock control section 105c distributes an externally supplied clock 111 to the inside of a CPU section 101 and a BCU section 105. During a read access request from the CPU section 101 to a storage device 106, the period of a CPU clock 112 supplied to the CPU section 101 is extended. That is, the state immediately before the change point of the CPU clock 112 when the CPU section 101 inputs input data via an internal data bus 104 is extended until read data has been established on the internal data bus 104.

Growing community of inventors

Tokyo, Japan

Hideki Sugimoto