Hitachi, Ltd.

Hideki Sakakibara

Toru Kobayashi

Yuji Yokoyama

Shuichi Miyaoka

Michiaki Nakayama

Kozaburo Kurita

Hideo Sawamoto

Mitsugu Kusunoki

Masaji Kume

Yuko Ito

Ryusuke Sahara

Koki Tsutsumida

Tomoji Nakamura

Yasuyoshi Sunaga

Atsushi Hazeyama

Yuuji Suzuki

Kazumasa Takashima

Nobutaka Itoh

There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S) and a predetermined linearity condition (S).

Semiconductor integrated circuit

The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal. A first signal and a second signal supplied from outside through a first signal path and a second signal path are respectively transferred to the pulse generator. When a rising time up to the full amplitude at any one of buffers in the first signal path and the second signal path is longer than a pulse width of a pulse to be formed by the pulse generator, the difference in phase between the first signal and the second signal is caused to correspond to a pulse width of a first pulse.

Semiconductor integrated circuit device

Read buffers (RB -RB ) are capable of holding data read out from a plurality of memory blocks (BNK -BNK ) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means ( ) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

Semiconductor integrated circuit device with memory blocks and a write buffer capable of storing write data from an external interface

Semiconductor integrated circuit device with memory banks and read buffer capable of storing data read out from one memory bank when data of another memory bank is outputting

A semiconductor integrated circuit device has a memory array which includes amplifying MOSFETs of sense amplifiers which amplify small voltages read out of dynamic memory cells onto bit lines and column switch MOSFETs which select bit lines, a read/write section which includes main amplifiers for reading out stored data from memory cells selected by the column switch, and a logic circuit which implements the input/output operation of data with the read/write section. Two capacitors each having a first electrode which corresponds to a plate electrode with the same structure as that of storage capacitors of dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors are arranged in serial connection, disposed contiguously to the read/write section, and connected between operation voltage lines of the read/write section.

Semiconductor integrated circuit device having stabilizing capacitors connected between power lines of main amplifiers

Growing community of inventors

Tachikawa, Japan

Hideki Sakakibara