Intel Corporation

Hideki Saito

Milind Baburao Girkar

Xinmin Tian

Sanjiv M Shah

Hong Wang

Wei Ey Li

John Thomas Shen

Perry H Wang

Daniel M Lavery

Gerolf F Hoflehner

Shih-wei Liao

Grant E Haab

Dongkeun Kim

Arun Kejariwal

Utpal Banerjee

A method for improving parallel processing of computer programs. DOACROSS loops and similar code are identified and parallelized using a post-wait control structure. The post-wait control structure may be implemented to include any one of a single counter to enforce an order of execution, an array to track code completion that is indexed by a modulus of a positive integer number, and/or a set of arrays to track a last code completed by a thread and a current code being executed by a thread.

Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processors

Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce performance bottlenecks due to memory latency and/or a cache miss. A performance analysis tool is used to profile the software application's resource usage and identifies areas in the software application experiencing performance bottlenecks. Compiler-runtime instructions are generated into the software application to create and manage the helper thread. The helper thread prefetches data in the identified areas of the software application experiencing performance bottlenecks. A counting mechanism is inserted into the helper thread and a counting mechanism is inserted into the main thread to coordinate the execution of the helper thread with the main thread and to help ensure the prefetched data is not removed from the cache before the main thread is able to take advantage of the prefetched data.

Methods and apparatus for reducing memory latency in a software application

Growing community of inventors

Sunnyvale, CA, United States of America

Hideki Saito