Hitachi, Ltd.

Elpida Memory, Inc.

Renesas Technology Corp.

Other

Renesas Electronics Corporation

Hitachi-high-technologies Corporation

Hitachi Automotive Systems, Ltd.

Ps4 Luxco S.a.r.l.

Hitachi, Ltd., Intellectual Property Group

Hideki Osaka

Yutaka Uematsu

Yoji Nishio

Tsutomu Hara

Toshihiko Ogura

Toyohiko Komatsu

Koichi Okazawa

Tsunehiro Tobita

Takashi Oeda

Ryuichi Hattori

Seiji Funaba

Susumu Hatano

Akira Yamagiwa

Kazuya Ito

Masaya Umemura

Satoshi Muraoka

Koichi Kimura

Satoru Watanabe

Takashi Tsunehiro

Takayuki Ono

Toshio Sugano

Tadanobu Toba

Eiichi Suzuki

Yukitoshi Hirose

Hitoshi Ueno

Akio Idei

Masabumi Shibata

Michinori Naito

Yuichi Fukuda

Takashi Miyagawa

Hiroshi Kakita

Taishi Sumikura

Masashi Horiguchi

Makoto Torigoe

Tatsuya Saito

Mitsuaki Katagiri

Takashi Suga

Hiroki Funato

Ryoichi Kurihara

Toshitsugu Takekuma

Kenichi Shimbo

Hitoshi Yokota

Shinichi Suzuki

Yuusuke Fukumura

Masao Inoue

Kazuyoshi Shoji

Tomonori Sekiguchi

Osamu Nagashima

Ichiro Anjo

Takashi Matsumoto

Yoshihiro Kondo

Toshiro Takahashi

Tatemi Ido

Satoshi Nakamura

Kenichi Ishibashi

Yukihiro Seki

Shunichi Saito

Keisuke Fukumasu

Yoshiyuki Tsuchie

Masahiro Toyama

Mitsuhiro Masuda

Kazunori Nakajima

Hidefumi Ibe

Katsunori Hirano

Kenichi Saitou

Yuichi Sakurai

Kenji Kashiwagi

Ken Iwakura

Masahiro Kitano

Masatsugu Shinozaki

Shigemi Adachi

Koichiro Aoki

Yusuke Fukumura

Tetsuo Hiramitsu

Yoshitsugu Ichieda

Hiroyuki Hodo

Mihoko Kudou

Tatusya Saito

Ken Iizumi

Provided is an electronic control unit, which includes a printed wiring board on which a semiconductor element is mounted, including a power supply pattern and a ground pattern which are formed on the printed wiring board and connected to the semiconductor element, at least one capacitance adjustment pattern which is formed on the printed wiring board, and a connection portion which is provided for each capacitance adjustment pattern and able to switch electrical connection between either the power supply pattern or the ground pattern and the capacitance adjustment pattern.

Electronic control device, vehicle, and method for manufacturing electronic control device

Provided is a semiconductor inspection circuit which is capable of inspecting connection states of power supply, ground, and signal bumps in a semiconductor package or a printed circuit board equipped with a semiconductor LSI mounted in a product operation state. As a means to solve the problem, a circuit capable of switching a path is provided at an input portion of a driver/receiver, a mechanism capable of transferring an output of a path switching circuit near a receiver circuit to a voltage waveform circuit with an internal variable terminal is provided, and a breakage state of a bump can be observed in the product operation state by observing a DC level at a terminal having a certain DC resistance when a signal bump connection state is observed and receiving a step wave and observing a response waveform thereof when an IO power supply bump connection state is observed.

Semiconductor device and multi-chip module

A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.

Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein

In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.

DRAM having SDRAM interface and flash memory consolidated memory module

When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal.

DRAM with SDRAM interface, and hybrid flash memory module

A simulation apparatus includes a discrete events simulation section to perform a discrete type simulation of components of a configured model as defined based on attribute information that is information on parts of the components of the defined configured model and connection information showing a connectional relationship among the components of the defined configured model; and a soft error rate computation processing section to compute a soft error rate of the defined configured model based on the simulation result of the discrete events simulation section and data on soft error rates in the attribute information.

Simulation apparatus and simulation method for determining soft error rates for a configured model

Provided is a noise equivalent circuit for completing an EMC analysis in a practical time and through a low-cost calculation process at an upstream stage of system design. The noise equivalent circuit includes one or more energy sources; a propagation path for propagation of energy from the energy source including a conductive path such as a cable and an electromagnetic field coupling path due to the coupling of an electric field and a magnetic field with another electronic device or cable; and a GND port connected to a system, and each port is represented by the noise voltage source or the noise current source and the internal impedance. This noise equivalent circuit can determine an external impedance that is varied depending on a load connected externally or the distance from an external device or a cable, whereby the noise of the system as a whole can be analyzed.

Noise equivalent circuit

Provided is a data processing device with which, when a temporary network congestion occurs, it is possible to avoid a buffer overflow and sustain a process. When a request for retransmission of the same data with respect to a processor element from a buffer occurs continuously a prescribed number of iterations, a data processing device according to the present invention determines that it is possible that a buffer overflow occurs, and suppresses an increase in the volume of data which is accumulated in the buffer (see FIG.).

Data processing device, semiconductor external view inspection device, and data volume increase alleviation method

A semiconductor device having a chip-on-chip structure is constituted of a first semiconductor chip and even-numbered pairs of second semiconductor chips, all of which are laminated together on the surface of an interposer. The first semiconductor chip controls each pair of the second semiconductor chips so as to activate one second semiconductor chip while inactivating another second semiconductor chip. The second semiconductor chips are paired together in such a way that through-vias and electrodes thereof are positioned opposite to each other via bumps. Since drive voltage electrodes supplied with a drive voltage (VDD) and reference potential electrodes supplied with a reference potential (VSS) are mutually connected together between the paired second semiconductor chips, it is possible to increase the overall electrostatic capacitance of each second semiconductor chip so as to substantially reduce feed noise without increasing the overall layout area of the semiconductor device.

Semiconductor device

An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

Test method and interposer used therefor

To provide a simulation technology of ending multiphysics analysis on heat, vibration, and EMC within a practical time and with a low-price computation process at an early stage of product designing, in a noise analysis designing method for an electric device, such as an inverter for automobile, this electric device includes one or more energy sources, a propagation path through which energy from the energy source propagates, and a noise occurring part where an electromagnetic radiated noise occurs due to the energy coming from the propagation path, the method has a step of estimating the occurring noise, such as a occurring radiated noise, by analyzing a path specified by a user by using a calculator, and the path specified by the user is a path of the energy flowing through the propagation path.

Noise analysis designing method

An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

Support method and apparatus for printed circuit board

A semiconductor chip and a semiconductor device mounting the semiconductor chip capable of increasing a capacitance of a capacitor without reducing the number of signal bumps or power bumps of a package and the number of Csolder balls of the semiconductor chip, and achieving a stable power supply with suppressing fluctuations of power at a resonance frequency without a limitation in a position to mount a capacitor for lowering noise of a signal transceiving interface block. In the semiconductor device, a via hole is provided to the semiconductor chip, a power-supply electrode connected to the via hole is provided to a back surface of the semiconductor chip, and a capacitor is mounted to the electrode on the back surface. And, a high-resistance material is used for a material of a power-supply via hole inside the semiconductor chip, thereby increasing the resistance and lowering the Q factor.

Semiconductor device with power noise suppression

A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 &#x3bc;m therebetween.

Semiconductor device and wiring part thereof

As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.

Low noise semiconductor device

Growing community of inventors

Oiso, Japan

Hideki Osaka