Sanyo Electric Co., Ltd.

Horiba, Ltd.

Semiconductor Components Industries, LLC

Nintendo Co., Ltd.

Sanyo Semiconductor Co., Ltd.

Hideki Ohashi

Takeo Inoue

Kuniaki Ito

Yasuyuki Shimohata

Kozo Okuda

Takeshi Yamada

Masahiro Tanimoto

Iwao Honda

Takashi Kuroda

Noriyuki Tomita

Kimikazu Yoda

Masahisa Shimizu

Takao Imaki

Hitoshi Hirai

Yoshitaka Onaya

Sumio Shimizu

Kenichi Uchida

Mituyoshi Fukuda

Masaki Kawaguchi

Shinsaku Yamada

Toshio Mizutaka

Hiroaki Katumata

An example system includes: a communication device including a first wireless communication part performing short-distance wireless communication; and an information processing apparatus including a second wireless communication part performing short-distance wireless communication, a processing part performing processing concerning input or output of information, a restriction part, in correspondence to the processing of one of the second wireless communication part and the processing part, restricting the processing of the other, and an information processing part performing information processing corresponding to a processing result of the second wireless communication part or the processing part whose processing is not restricted by the restriction part.

Information processing system, game system, information processing apparatus, recording medium, and information processing method

An example system includes: a communication device having a first wireless communication unit for sending and receiving data to and from an information processing apparatus through short-distance wireless communication; and an information processing apparatus having a second wireless communication unit for sending and receiving data to and from the communication device through short-distance wireless communication, a detector for detecting existence of the communication device in an effective communication area of the second wireless communication unit, an acceptance unit for accepting detection or non-detection by the detector as an input operation by a user, and an information processor for performing information processing in accordance with the input operation accepted by the acceptance unit.

Information processing system, game system, information processing apparatus, recording medium and information processing method

An echo prevention circuit comprises an input terminal to which a first input signal is input; a first FIR filter into which the first input signal is input through the input terminal; a second FIR filter into which the first input signal is input at the same time as into the first FIR filter; an input/output terminal to which an output signal of the first FIR filter is output or a second input signal is input; a subtracter that subtracts an output signal of the second FIR filter from a combined signal of the output signal of the first FIR filter and the second input signal; and an output terminal to which an output signal of the subtracter is output. The first and the second FIR filters have such filter coefficients that the output signal through the output terminal has only the output signal from the first FIR filter removed.

Echo prevention circuit having signal subtracter feature

A filter coefficient setting device for setting a filter coefficient of an echo prevention device including a first FIR filter, and a second FIR filter, comprises: a filter coefficient initial setting portion configured to set a predetermined filter coefficient for the first and second FIR filters when the echo prevention device is started.

Filter coefficient setting device and echo prevention device

An echo prevention circuit comprises a first and second FIR filters into which a first input signal is input through an input terminal; an input/output terminal to which an output signal of the first FIR filter is output and the output signal reflected is input or a second input signal is input; a first subtracter that subtracts an output signal of the second FIR filter from a combined signal of the output signal of the first FIR filter and the second input signal; an adaptive digital filter into which the output signal of the first FIR filter is input; a second subtracter that subtracts the output of the adaptive digital filter from the output of the first subtracter. The adaptive digital filter has such filter coefficients that based on the output of the second subtracter, the output signal from the output terminal is the output from the first subtracter that has had the other than the second input signal removed.

Echo prevention circuit having adaptive digital filter

An encoding circuit is disclosed which comprises: a data-for-encoding storing register that stores n-bit data for encoding; a data-for-calculation storing register that stores m-bit data for calculation generated by shifting the data for encoding; a shifter that shifts the data for encoding stored in the data-for-encoding storing register, and shifts and inputs the shifted data into the data-for-calculation storing register; a first coefficient register that stores m-bit first coefficient data indicating a first coefficient for executing encoding; a first logic circuit that is inputted with the data for calculation stored in the data-for-calculation storing register and the first coefficient data stored in the first coefficient register and outputs the logical product for each bit of the data for calculation and the first coefficient data; and a second logic circuit that is inputted with m-bit data outputted from the first logic circuit and outputs the exclusive logical sum of the m-bit data as the encoded data.

Encoding circuit and digital signal processing circuit

A memory control circuit that controls m (=L/k) memories (first to mth memories), each of which has a k-bit width, the m memories storing data having a data width (D bits) of an integral multiple of k bits up to L bits, the circuit comprising: an address input circuit that determines a memory (nth memory) storing a first k bits of the data among the m memories, based on a start-position specification address which is a predetermined j bits of an A-bit address indicating a storage destination of the data, and inputs to the nth to mth memories a first specification address for specifying a storage destination of the data, the first specification address being an A-j bits of the A-bit address, which is the A-bit address without the predetermined j bits thereof, and inputs to the first to (n&#x2212;1)th memories a second specification address obtained by adding one to the first specification address; a data input circuit that inputs a plurality of pieces of divided data obtained by dividing the data into k-bit data to the memories respectively, in the order of the nth to mth memories and the first to (n&#x2212;1)th memories, based on the start-position specification address; a data output circuit that reads the plurality of pieces of divided data from the memories respectively, in the order of the nth to mth memories and the first to (n&#x2212;1)th memories, the number of the memories corresponding to the data width of the data, and outputs the read plurality of pieces of divided data as the data, based on the start-position specification address; and a memory selecting circuit that makes the D/k memories readable/writable, in the order of the nth to mth memories and the first to (n&#x2212;1)th memories, based on the start-position specification address and the data width of the data.

Memory control circuit and memory control method

Echo preventing circuit includes first and second FIR filters. The outputs of the first and second FIR filters are converted into first and second analog signals. An input/output terminal outputs the first analog signal or receives a third analog signal. An AD converter converts an analog signal obtained by subtracting the second analog signal from a signal formed by combining the first analog signal and the third analog signal. A response signal acquiring unit acquires a first response signal from an output of the first FIR filter to an output of the AD converter. A filter coefficient setting unit sets the filter coefficients of the second FIR filter based on the first response signal and sets the filter coefficients of the first FIR filter based on second response signal of a section from and output of the second FIR filter to an output of the AD converter.

Apparatus and method for setting filter coefficient, and recording medium having a program recorded thereon

An echo prevention circuit includes a filter that receives a first digital signal and outputs second and third digital signals; first and second DA converter that convert the second and third digital signals into first and second analog signals respectively; a circuit to subtract the second analog signal from a signal generated by combining the first analog signal and a third analog signal, a circuit to amplify the signal from the subtracting circuit; an AD converter that converts the amplified signal into a digital signal; a responsive signal acquiring unit to acquire a first response signal from the input of the first DA converter to the output of the AD converter and to acquire a second response signal from the input of the second DA converter to the output of the AD converter; and a unit to set filter coefficients based on the first and second response signals.

Echo prevention circuit, filter coefficient setting method, and recording medium with program recorded

A gas sampling bag is capable of blowing out the gas uniformly into the bag main body, and filling the bag main body with gas in a securely mixed state. A gas sampling bag that is connected to a constant volume sampling passage, contains a pipe, on which a plurality of gas inlet/outlet holes are formed, in a bag main body, and allows the gas to flow into/out of the bag main body through the gas inlet/outlet holes. The opening of the plurality of gas inlet/outlet holes is formed in such a manner that the size is minimized while the pressure loss is suppressed so as not to increase as far as possible.

Gas sampling bag

An echo preventing circuit comprises a filter that is inputted with a first digital signal and outputs a second and a third digital signals; a first DA converter that converts the second digital signal into a first analog signal and outputs the first analog signal; a second DA converter that converts the third digital signal into a second analog signal and outputs the second analog signal; an input/output terminal that outputs the first analog signal or that is inputted with a third analog signal; a subtracting circuit that outputs a fourth analog signal obtained by subtracting the second analog signal from a signal formed by combining the first analog signal and the third analog signal; and an AD converter that converts the fourth analog signal into a fourth digital signal and outputs the fourth digital signal, wherein the filter sets filter coefficients for which the fourth analog signal is a signal formed by removing or attenuating the first analog signal from a signal formed by combining the first analog signal and the third analog signal, based on the fourth digital signal outputted from the AD converter when signals are inputted into the first and the second DA converters while the third analog signal is not present, and wherein the fourth analog signal outputted from the subtracting circuit is outputted as an output signal corresponding to the third analog signal.

Echo preventing circuit and digital signal processing circuit

A detachable gas analyzing apparatus has a plurality of gas analyzer units insertable into and removable from a the front side of a container case. Complementary electrical and gas connectors are disposed on the rear side of the gas analyzer units and the container case. Guides and engaging rails guide the gas analyzer units as they are inserted into the container case. The gas connectors are substantially self-aligning by the provision of complementary tapered portions formed on gas sockets and plugs. The gas connectors also align the electrical connectors and provide compensation for linear misalignment. A plurality of gas connectors may also be employed, forming a number of inward and outward gas passages.

Detachable gas analyzing apparatus

A data input/output circuit includes a 32-bit reversible shift register (1) which includes four 8-bit reversible shift registers (2-5). Input gate circuits (6, 7) selectively apply data being inputted in a bit-serial fashion from an external to the 8-bit reversible shift registers (3, 4), and output gate circuits (8-12) selectively output data being stored in arbitrary stages of the 32-bit reversible shift register (1) in a bit-serial fashion. Input latches (13-15) and output latches (16-18) each of which is an 8-bit latch are connected to the respective 8-bit reversible shift registers (2-4) and a data bus (19). The input latches (13-15) hold the data being stored in the 8-bit reversible shift registers (2-4) and send the same onto the data bus (19) in a bit-parallel fashion, and the output latches (16-18) hold the data being sent from the data bus (19) and preset the same into the 8-bit reversible shift registers (2-4) in a bit-parallel fashion.

Data input/output circuit for a digital signal processing system

A crucible cassette for use in feeding crucibles to an apparatus for loading and feeding crucibles to a combustion furnace, said cassette having at least one crucible receiving tube capable of receiving a plurality of crucibles stacked one above the other, an engaging member in the bottom of the tube for engaging with the lowermost crucible and supporting it in the receiving tube and a guide member for guiding the rise of the crucibles in the tube, and a pusher for pushing crucibles one by one up out of said tube to enable them to be carried one by one from the cassette means to a sample weighing position in the apparatus.

Growing community of inventors

Kyoto, Japan

Hideki Ohashi