Hitachi, Ltd.

Hideki Murayama

Takehisa Hayashi

Hiroshi Yashiro

Satoshi Yoshizawa

Hiroshi Iwamoto

Yasuhiro Ishii

Kazuo Horikawa

Masahiko Yamauchi

Takeshi Aimoto

Hidenori Inouchi

Daisuke Sasaki

Kimitoshi Yamada

Masahiro Kitano

Kazuhiro Hashimoto

Tsutomu Goto

Hiroshi Ohguro

Haruyuki Nakayama

Hirofumi Fujita

Shoichi Murase

Shinichi Tanabe

Kenji Nakajima

Akira Yamagiwa

Naoki Hamanaka

Kenichi Ishibashi

Tetsuhiko Okada

Masabumi Shibata

Toru Horimoto

Atsushi Ugajin

Akira Kito

An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.

Information processing apparatus

Memory managing method used in adding memory and information processing apparatus

A computer system having a plurality of computers connected to each other by a computer coupling mechanism. Each computer includes a processor, memory, I/O device, disk control mechanism, computer coupling network adapter, disk requirement processing section connected to a system bus, and a disk connected to a disk control mechanism. The disk requirement processing section controls the disk, in response to a processing requirement for the disk from one of the processors of the other computers, based on structural definition information. The structural definition information describes a structure of the computer system. The computer system may be a loosely-coupled computer system.

Computer system having a plurality of computers each providing a shared storage access processing mechanism for controlling local/remote access to shared storage devices

Before transferring data, a transmitting computer acquires a transfer rate of an I/O bus to which a communication control device in a receiving computer is connected. When transmitting data, the communication control device refers to a connection control table and a receiver control table, and chooses a transmitting queue for data transmission from a plurality of transmitting queues so that an interval is inserted between transmissions of data, and the data can be transmitted to the receiving computer without loss. The transmission intervals of data are determined based on the transfer rate of the I/O bus to which the communication control device in the receiving computer is connected.

Communication control device transmitting data based on internal bus speed of receiving computer

A control method of controlling a computer for controlling a resource connected to the computer and shared by a plurality of programs included in the computer includes the steps of storing a control information ID indicating a storage area in the main memory storing control information concerning access between a certain program and the resource in an OS space of a main memory, storing the control information ID in an adaptor connected to the main memory via a bus, and taking out the control information from the storage area included in the OS space, by using the control information ID stored in the adapter. In the case where the adapter runs short of a storage area, information that the adapter runs short of a storage area in the main memory is conveyed via the bus. By using the control information thus taken out, the resource is controlled.

Method and apparatus for controlling resource

A memory disc sharing method in which a plurality of computers share a memory disc through a network, wherein a command in accordance with which the memory disc is accessed is received by a network interface apparatus, and when a requested computer to which a request of the command has been made is any of other computers, the command is transmitted to the any of other computers, and when the requested computer is a computer concerned, the command is stored in a memory disc command queue. The network interface apparatus retrieves the command from the memory disc command queue, and executes the processing of reading out/writing data from/to the memory disc in the computer concerned when a requesting computer from which a request of the command has been made is the computer concerned, and carries out the data transfer between the memory disc in the computer concerned and the requesting computer when the requesting computer is any of other computers.

Memory disk sharing method and its implementing apparatus

A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs. When receiving the output resistance value adjustment request signal, the output resistance value adjustment units stop the signal transmission between the LSIs, adjust output resistance values of output circuits in such a manner that the output resistance values are matched with a characteristic impedance of a transmission line, and maintains the adjusted output resistance values until the output resistance value adjustment units receive next output resistance value adjustment request signal.

Semiconductor integrated circuit system having function of automatically

Computer system having a plurality of computers each providing a shared

A data communication system for a computer system in which a plurality of computers are mutually connected includes: a plurality of computers each having an area to store a command to execute a data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the plurality of computers; and a transmission permitting component, connected between the switch circuit and one of the plurality of computers, for outputting a signal to permit the data transmission from such one computer to such another computer; a communication component for transmitting the data received from such one computer by outputting the transmission permission signal from the transmission permitting component to such another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from such one computer to such another computer; and a communication control component to abandon the data that is subsequently received from such one computer by outputting the transmission permission signal in accordance with an output of the detecting component. When the abnormality occurs, the switch circuit releases such another computer, thereby disconnecting such one computer and such another computer. When reception commands prepared in the buffer area of such another computer are perfectly used, such another computer abandons the packet which does not include the flag to instruct the continuous reception.

Network for mutually connecting computers and communicating method using

A data communication system for a computer system in which computers are mutually connected includes: each computer having an area to store a command to execute data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the computers; and a transmission permitting component, connected between the switch circuit and one of the computers, for outputting a signal to permit the data transmission from one computer to another computer; a communication component for transmitting the data received from one computer by outputting the transmission permission signal from the transmission permitting component to another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from one computer to another computer; and a communication control component to abandon the data that is subsequently received from one computer by outputting the transmission permission signal in accordance with an output of the detecting component. When the abnormality occurs, the switch circuit releases another computer, thereby disconnecting one computer and another computer. When reception commands prepared in the buffer area of another computer are perfectly used, another computer abandons the packet which does not include the flag to instruct the continuous reception.

A system for controlling the DMA transfer for a plurality of IO devices has an IO controller for each group of the IO devices. Data is retrieved from memory and stored in the IO controller where it is analyzed. The retrieved data has a structure that permits a group of DMA start request quads to be linked together for parallel or pipeline processing of the DMA transfer requests. Each start request quad has a pointer for additionally retrieving corresponding command data. The command data is set forth in a number of blocks, each linked to the next one by a pointer. When a DMA processing has been completed, the termination or completion status is entered into a specific entry in a completion list for the corresponding IO device. Thus, a determination can be made as to whether specific IO devices have completed a requested DMA processing. Expansion of the system is accomplished by using combinations of main and sub controllers, where one main controller provides the aforementioned data structures for many sub controllers in order to enable the DMA processing to be performed for IO devices connected to the sub controllers with less frequent access of system main memory and the system bus.

Input/output control method and data processor

A distributed shared memory management system for a distributed shared memory computer system having a plurality of computers interconnected by a network, each computer having an independent address space and logically sharing data physically distributed to a storage of each computer. Each computer running a program for reading/changing the shared data includes a coherence control designation command for designating to enter a mutual exclusion state in which two or more computers cannot change the logically single shared data, a coherence control release command for designating a release of the mutual exclusion state, and a coherence control execution command for reflecting the contents of the shared data changed between the coherence control designation command and the coherence control release command, upon the logically single shared data in another computer. At least one of the plurality of computers includes a request message queue for storing a coherence control request message issued by the coherence control execution command when the coherence control designation command is executed. The coherence control designation command includes data for designating the order of reading/changing the shared data, and the request message queue includes a counter for storing a current state regarding the control of the order of reading/changing the shared data and a unit for storing a value regarding the control of the order of reading/changing the shared data.

Distributed shared data management system for controlling structured

The present invention relates to a network communication method and a network system that enables received data to be transferred directly to the user data region, thereby eliminating the need to perform data copy operations. In the present invention, packets are each provided with received region assignment information (port ID) for showing the region in which the packet is to be received and/or division information for dividing the packet. The region which is to receive data contained in the packet is determined from a port table and conversion tables, and the packet data is transferred to the region directly.

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Kunitachi, Japan

Hideki Murayama