Sharp Kabushiki Kaisha Corporation

Hideki Morii

Akihisa Iwamoto

Takayuki Mizunaga

Toshihiro Yanagi

Hidekazu Miyata

Satoshi Horiuchi

Takaharu Yamada

Kazushige Miyamoto

Kei Ikuta

Yuuki Ohta

Masahiro Hirokane

Kazuya Nakaminami

Yuta Ueyama

Shinya Tanaka

Tetsuo Kikuchi

Masami Ozaki

Yuhko Hisada

Ryohki Itoh

Hirofumi Miyamoto

Yukihisa Orisaka

Masakazu Takeuchi

Chikao Yamasaki

Toru Kuriyama

A charge pull-out period is set after power off, and an all-on control signal is set to a high level in the charge pull-out period. A high-level voltage which is output to a scanning line drive circuit formed on a liquid crystal panel is kept at a high level even after power off until a middle of the charge pull-out period. A common electrode control circuit for connecting a common electrode to a ground when the all-on control signal is at the high level and the high-level voltage is at an operation level is configured using two resistors, a NOT circuit, and two FETs, and is provided to a liquid crystal display device. With this, a liquid crystal display device which can lower a common electrode voltage to a ground level when power off and can prevent burn-in after power on is provided.

Liquid crystal display device including common electrode control circuit

The liquid crystal display device includes a liquid crystal panel including a display area for displaying images and a non-display area other than the display area, a rigid board configured to connect with an external signal source, and a flexible board. The liquid crystal panel and the flexible board are arranged in a first direction. A direction perpendicular to the first direction and along a plate surface of the liquid crystal panel is a second direction. The flexible board is larger in a dimension in the second direction than the rigid board, and includes an end portion including at least an outer portion located outside of the rigid board in the second direction, and a middle portion located about a middle of the flexible board with respect to the end portion in the second direction. The end portion is larger in dimension in the first direction than the middle portion.

Display device

Provided are: a liquid crystal display device capable of rapidly removing residual electric charges in a panel when a power supply is turned off, and in particular, suitable for a case where IGZO-GDM is adopted; and a driving method of the liquid crystal display device. In the liquid crystal display device, when an OFF state of the power supply is detected, a power supply OFF sequence including an initialization step, a first discharge step and a second discharge step is executed. In the initialization step, only a clear signal (H_CLR) among GDM signals is set at a high level, and a state of each of bistable circuits which constitute a shift register is initialized. In the first discharge step, only the clear signal (H_CLR) among the GDM signals is set at a low level, all of gate bus lines are turned to a selected state, and electric charges in pixel formation portions are discharged. In the second discharge step, the clear signal (H_CLR) is set at the high level, and electric charges on floating nodes in each of the bistable circuits are discharged.

Liquid crystal display device and drive method for same

The invention provides a liquid crystal display device that includes an IGZO-GDM which can quickly remove a residual charge in a panel when the power supply is turned off, and a driving method of the liquid crystal display device. Each bistable circuit that configures a shift register includes a thin film transistor TI for increasing a potential of an output terminal based on a first clock, a region netA connected to a gate terminal of the thin film transistor TI, a thin film transistor TC for lowering a potential of the region netA, and a region netB connected to a gate terminal of the thin film transistor TC. In such a configuration, a power supply off sequence includes a display off sequence and a gate off sequence. The gate off sequence includes at least a gate-bus-line discharge step (tto t), a netB discharge step (tto t), and a netA discharge step (tto t).

Liquid crystal display device and driving method thereof

A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts. This configuration achieves a display panel drive circuit which prevents display disorder or holds down increase in load given to a power source, each of which occurs in a case where anomalousness is included in the sync signal.

Shift register and liquid crystal display device for detecting anomalous sync signal

A display device, in at least one embodiment, includes: a gate driver including a plurality of shift register stages each provided so as to correspond to each row, the gate driver outputting a gate signal for turning on switching elements in the each row; and a source driver outputting a data signal in accordance with an image to be displayed. For a row (first row) located at an outermost position from which scanning by use of the gate signal starts, a dummy line is provided. The dummy line is driven by a gate start pulse inputted into a shift register in the first row.

Display device for reducing parasitic capacitance with a dummy scan line

In one embodiment of the present invention, in an even-numbered signal line group, the arrangement sequence of the first and second signal lines is reversed between in a display area and in a non-display area, and the same goes for the arrangement sequence of the third and fourth signal lines. The ends of the first to sixteenth signal lines in the non-display area are connected to the first to sixteenth individual drivers, respectively. An odd-numbered individual driver and an even-numbered individual driver each output a corresponding one of drive signals of opposite polarity. Thus, the polarities of subpixels of the same color arranged in a first direction D(horizontal direction) differ between the subpixels connected to the odd-numbered signal line group and the subpixels connected to the even-numbered signal line group. That is, all of the subpixels having the same color arranged in the horizontal direction do not have the same polarity. This helps reduce a horizontal shadow.

Display device and method for driving display member

An object is shortening a clock fall-rise period while suppressing an increase in a circuit area, an increase in current consumption, and a cost increase, without generating an abnormal operation, in a shift register within a monolithic gate driver. In a shift register () that operates based on four-phase clock signals, including two-phase clock signals (GCK, GCK) that are provided to odd-order stages and two-phase clock signals (GCK, GCK) that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock (CKA) appears as a potential of a scanning signal (GOUT), when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.

Shift register, scanning signal line drive circuit provided with same, and display device

Each stage that constitutes a shift register includes an output-control thin-film transistor for increasing a potential of a scanning signal based on a first clock (CKA), two thin-film transistors for increasing a potential of a first node connected to a gate terminal of the output-control thin-film transistor, based on a scanning signal outputted from a pre-stage/a latter stage, and two thin-film transistors for decreasing a potential of the first node, based on a scanning signal outputted from a third stage after/a third stage before a stage concerned. The shift register operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other.

A liquid crystal display device includes: scanning wires, provided so as to correspond to a plurality of pixels disposed in a matrix manner, to which scanning signals are applied; and signal wires to which data signals are applied, wherein the scanning wires and the signal wires cross each other. TFTs, electrically connected to the scanning wires and the signal wires, each of which is provided in the vicinity of an intersection of the scanning wire and the signal wire, and the TFTs are connected to pixel electrodes. A dummy pixel driven by a dummy signal wire is provided externally adjacent to an endmost pixel column. This brings about a matrix type liquid crystal display device that equalizes capacitive conditions of all the signal wires to each other and can prevent deterioration of display quality that is brought about by a specific portion differently displayed.

Liquid crystal display device

In one embodiment of the present invention, a video signal processing method is disclosed wherein video correction data is read from a ROM and written into an LUT, and the video correction data written in the LUT is used to perform data correction of an externally inputted video signal. The video correction data written in the LUT is updated during the horizontal blanking interval of the video signal.

Video signal processing method, video signal processing apparatus, and display apparatus

In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate Sx which is a change quantity per unit time, and by desirably setting the change rate Sx, a change rate Sxin the vicinity of an input-side end of the scanning signal line and a change rate SxN in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(, j) and Vg(N, j).

Display device and display method

In a display device of the present invention, during a period until the start of outputting display data from a source driver, a timing control ASIC generates a gate start pulse signal GSP and a first pulse CKof a gate clock signal GCK, with reference to the timing of inputting a data enable signal ENAB. The signals having been generated are supplied to the gate driver, so that a dummy line Gis driven.

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Osaka, Japan

Hideki Morii