Fujitsu Corporation

Hideki Miyasaka

Tetsuya Yasui

Hiroshi Ohtsuru

Takahiro Hosokawa

Yuji Mori

Yoshitsugu Nishizawa

Yuji Takenaka

Kimihiko Kazui

Hideaki Watanabe

Yukio Otobe

Hirohiko Inagaki

Katsuki Miyawaki

Masao Mutou

Takehira Masanori

Yasunori Ueno

Kouji Maruyama

Kiyoshi Maeda

A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.

Video signal receiver with level limited output

An encoding unit encodes and compresses picture data in a bit map format corresponding to the MPEG method. A packet assembling portion assembles the picture data encoded by the encoding unit as packets in the format corresponding to the MPEG method, and stores the packets to a storing medium. At this point, the packet assembling portion writes an I picture index to a packet that contains at least a part of I picture data. When a special reproducing operation is performed, a data storing unit reads only packets that have the I picture index. A decoding unit decodes only I picture data of picture data contained in packets read from the storing medium and displays the decoded picture data.

Moving picture data storing system and moving picture data decoding

Control operations to access a memory changes respective priorities of the operations depending on the situation of the memory, and the operations are arbitrated and scheduled according to the respective, changed priorities, in order to avoid concentration on or rejection of a specific memory access operations and to eliminate an ineffective period. This realizes an efficient memory system without increasing the capacity of a buffer memory, the width of a memory bus, or an operating frequency.

Method controlling memory access operations by changing respective

Moving image coding apparatus and moving image decoding apparatus

An image data coding system, wherein an image data in a bit map form is divided into first and second groups, pixels in each group of which are distributed over the whole area of the image data in the bit map form. First and second coders respectively code the first and second groups of image data into first and second groups of coded image data. The first and second groups of image data in the original image data are respectively input into first and second memories, respectively. Blocks of the first group of image data are supplied to the first coder at first times, respectively, and blocks of the second group of image data are supplied to the second coder at second times, respectively. Boundaries of the blocks in the first group of image data are located in different positions from boundaries of the blocks in the second group of image data, and the first times are different from the second times. In the receiver side, first and second decoders respectively decode the above first and second groups of coded image data into first and second groups of decoded image data. By composing the first and second groups of decoded image data, the original image data in the bit map form is restored.

Block transformation coding and decoding system with offset block

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Kawasaki, Japan

Hideki Miyasaka