Renesas Electronics Corporation

Nec Electronics Corporation

Hideki Matsuyama

Masayuki Daitou

Nobuyasu Kanekawa

Masayuki Daito

Takashi Yasumasu

Hitoshi Arimitsu

The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part.

Microcontroller utilizing redundant address decoders and electronic control device using the same

A microcomputer includes: a plurality of register lists having a plurality of register patterns, respectively, wherein each of plurality of register patterns designates registers, data of which are to be saved in a data memory; an instruction fetch control circuit configured to fetch instruction code from an instruction memory in response to an interrupt request issued based on occurrence of an interrupt factor; and a register data saving control circuit configured to acquire one register pattern from one of the plurality of register lists in response to the interrupt request, and issue a microinstruction based on the acquired register pattern in response to the interrupt request. An instruction executing section is configured to execute the microinstruction prior to the fetched instruction code, to save the data of registers designated based on the acquired register pattern in the data memory.

Process and method for saving designated registers in interrupt processing based on an interrupt factor

Processor and method for saving designated registers in interrupt processing based on an interrupt factor

A processor system according to an exemplary aspect of the present invention includes a first processor, a second processor, a control unit, a signal line group, and a selection circuit. The control unit switches an operation mode between a lock step mode for the first and second processors to execute the same instruction stream and a free step mode for the first and second processors to execute different instruction streams. The signal line group includes at least one signal line disposed between a first memory circuit included in the first processor and a second memory circuit included in the second processor. The signal line group is capable of transferring a storage state of the first memory circuit to the second memory circuit. The selection circuit is capable of switching a connection destination of the second memory circuit between the second processor and the signal line group.

Processor system and operation mode switching method for processor system

Provided is a microprocessor including a complex-MAC unit that operates in response to a complex-MAC instruction. The complex-MAC unit receives first and second complex data (each having 2-bit length) from a first register having a register length of at least 2bits, and also receives third and fourth complex data (each having 2-bit length) from a second register having a register length of at least 2bits, to calculate a sum of real parts or imaginary parts of a complex product of the first and third complex data and a complex product of the second and fourth complex data. The complex-MAC unit adds the obtained sum of the real parts or imaginary parts to a stored value of the third register, and overwrites the third register with the cumulative total value. The third register has a register length of at least 2+2 bits.

Microprocessor

A filter operation circuit of a microprocessor executes an IIR filter operation by using data provided from registers Rto Rand outputs one sample of data Y[n] subjected to filter operation and transfer data P[n] to be used in the next IIR filter operation. Register Rprovides filter coefficients to the filter operation circuit. Register Rprovides past transfer data P[n&#x2212;1] and P[n&#x2212;2] to the filter operation circuit and is overwritten and updated with new transfer data P[n] output from the filter operation circuit. Register Rholds multiple samples of data X[n] to X[n+3] to be subjected to filter operation and provides X[n] to the filter operation circuit. An area of register Rin which X[n] has been held is overwritten and updated with Y[n].

Microprocessor performing IIR filter operation with registers

A data storing part outputs n-bit data according to a reading address generated by an address generator. A peak value candidate selecting part selects a maximum value of a plurality of elements forming the n-bit data as a peak value candidate when data of one data unit is expressed as one element and outputs the peak value candidate together with a positional information indicating an element position of the peak value candidate. When the peak value candidate is larger than a peak value held in a peak value holding part, a peak value calculating part calculates an address of the peak value candidate using the positional information of the peak value candidate and a reading address, outputs the address and the peak value candidate to the peak value holding part, and updates content held in the peak value holding part.

Microprocessor and method of processing data including peak value candidate selecting part and peak value calculating part

A bus system includes one or more bus masters, one or more bus slaves, and a response unit. When an access request to a resource of a bus slave is sent from a bus master, the response unit outputs a wait response that is either a blocking wait response to cause the bus master to perform a blocking wait operation or a non-blocking wait response to cause it to perform a non-blocking wait operation to the bus master if the bus slave is in the wait state.

Bus system, bus slave and bus control method

Memory protection apparatus to protect memory area to realize high interruption response and prohibit from access to the memory area that is previously designated. The memory area data registers() to (m), respectively, retain data which designate the accessible memory area in the processing corresponding to interruption of the group number corresponding to it. Selection circuitselects any of the memory area data registers() to (m) according to the group number retained by the group number register, and outputs data that designates selected memory area retained by the memory area data registers. Address bus watching partwatches generation of illegal memory access of the processor according to the data designating the memory area output by the selection circuit

Memory protection apparatus

Interrupt controlling circuit by which only a desired one(s) of plural interrupts may readily be masked. An interrupt factor controlling moduleis provided for each interrupt. An interrupt group setting registerholds a group number of an interrupt signal INT entered to the interrupt factor controlling module. An interrupt group mask registerholds, for each group, information as to whether or not an interrupt belonging to a group in question is to be masked. In case an interrupt has occurred and the group of the group number of the interrupt, as held by the interrupt group setting register, is specified by the interrupt group mask registeras being to be masked, the interrupt mask circuitmasks the interrupt.

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Kanagawa, Japan

Hideki Matsuyama