Fujitsu Corporation

Kabushiki Kaisha Toshiba

Hideki Matsui

Mitsuhiro Kawaguchi

Koji Takeguchi

Nobuhiro Rikitake

Shigeo Tani

Hirotaka Morita

Masahiro Shioda

Shosaku Yamasaki

Ryuichi Moriya

Katsuhiro Ono

Kazuhiro Shibuya

Mitsumasa Matsuike

Takashi Kaiga

Ryuji Kayama

Ryoji Azumi

Kuniaki Fujii

Ryuchi Moriya

Asuka Takano

Shouzo Takeno

Kazushige Sasaki

Kunio Doi

A generating unit that generates phase difference-added first data obtained by adding a phase change according to second data to a first signal indicating first data and a transmitting unit that transmits the phase difference-added first data are provided, and thus the first data and the second data can be transmitted through a simple configuration.

Communication control device and communication control system

First data and second data are transmitted by a simple configuration by including a generation unit that generates a wavelength-changed signal on the basis of the second data, and a transmission unit that transmits the wavelength-changed signal together with a first signal that indicates the first data.

A control device includes a first processor, a relay device, a second processor, and a third processor. The first processor is configured to perform data communications with an electronic device. The relay device is configured to relay the data communications. The relay device includes a buffer for storing data to be transmitted or received in the data communications. The second processor is configured to check a state of the buffer to detect a buffer full state in which the buffer is full. The third processor is configured to check a state of the first processor to detect a halt state in which the first processor has halted. The third processor is configured to reset the relay device upon detecting the halt state and upon the second processor detecting the buffer full state.

Control device and control method

A storage device includes one or more storages and one or more control devices to control writing data to and reading data from one of the storages. Each of the control devices includes a memory, a memory controller, and a processor. The memory controller controls writing data to and reading data from the memory. The processor determines whether the memory and the memory controller have error correcting functions respectively. The processor determines, when at least one of the memory and the memory controller does not have an error correcting function, whether an error is detected in first data expanded in a first memory region of the memory. The first data includes an error detecting code. The processor saves, when no error in the first data has been detected, the first data into a second memory region of the memory. The second memory region is different from the first memory region.

Storage device, control device and data protection method

A plug-in card storage device includes a plug-in card including a memory to store received input data and an error correction circuit to be equipped electrically connectable to the memory and to correct an error in the input data outputted from the memory; a device main body to have the plug-in card implemented therein; and a processor to determine whether or not to activate the error correction circuit, by calculating a reliability index value of the plug-in card based on an error rate of the memory provided in the plug-in card implemented in the device main body, so as to approximate the reliability index value to a reference value.

Plug-in card storage device and error correction control method thereof

There is provided a field programmable gate array (FPGA) mounted apparatus included in a first node of a plurality of nodes connected on a network, the FPGA mounted housing apparatus including a printed circuit board (PCB) on which an FPGA is mounted, and a controller configured to issue a request to acquire configuration data of the FPGA to a second node of the plurality of nodes, and configure the FPGA based on the configuration data acquired from the second node in response to the request.

FPGA mounted apparatus and FPGA configuration method

A data processing apparatus includes a first frame processing unit that fragments a first input frame and identifies a head of the first input frame and outputs first head position information; a second frame processing unit that fragments a second input frame which is a redundant frame of the first input frame and is input asynchronously with the first input frame, identifies a head of the second frame, and outputs second head position information; a first and a second storage unit that receive and store the fragmented pieces of data output from the first and the second frame processing units respectively; and a fragmented data processing unit that reads the fragmented pieces of data out of one of the first and second storage units based on the first and second head position information and outputs the fragmented data.

Data processing apparatus and redundancy switching method

A control apparatus controls a signal processing unit. The signal processing unit is mounted within a case and includes a waveform shaping unit which performs a waveform shaping process on an inputted signal. The control apparatus includes: an obtaining device which obtains (i) mounting information indicating a mounting state of the signal processing unit, (ii) temperature information indicating a temperature of the signal processing unit, and (iii) processing unit characteristic information indicating characteristics unique to the signal processing unit; and an adjusting device which adjusts waveform shaping characteristics of the waveform shaping unit, on the basis of the mounting information, the temperature information and the processing unit characteristic information.

Control apparatus and method, and signal processing apparatus

There is provided a time slot interchanger for processing channel setting data functioning as control data for interchanging time slots of multiplexed transmission data. In the time slot interchanger, processing of the channel setting data based on alarm data is performed in accordance with a preset first transmission capacity, and with respect to the channel setting data in accordance with a preset second transmission capacity, processing of the channel setting data in accordance with the first transmission capacity is dispersedly performed in a time series manner.

Time slot interchanger

There is provided a node apparatus having a plurality of interface units for interfacing to a transmission line, switch units of a work system and a protection system for switching signals of the transmission line, and a service selector used to relieve a network failure over ring networks interconnected by node apparatuses, the node apparatus including a first controller for controlling the service selector in the switch units, and a second controller for controlling setting information of alarm detection in case of using the service selector in the interface units.

Node apparatus interconnecting ring network

In a transmission apparatus, unlike in the conventional transmission apparatus, a protection switch is not arranged on the signal path, but a TSI having only the basic function performs the function of the protection switch as a substitute, a processing unit to perform the switching function at a low rate is artificially constructed on a TSI, the switch process of SONET protection type is artificially executed by the TSI, and a signal for controlling the TSI function is further controlled thereby to realize the protection switch function. The logic of switching at the main signal rate in addition to the conventional TSI function is deleted.

Transmission apparatus

In order to increase the efficiency of large-capacity transmission, the continuity of divided signals generated by dividing a multiplexed signal is maintained and the original large-capacity multiplexed signal is restored. A signal dividing section divides a multiplexed signal to generate a plurality of divided signals in the STS or STM transmission interface format. A guarantee information adding section adds guarantee information for guaranteeing the continuity of the divided signals to each of the divided signals to generate transmission signals. A signal sending section sends the transmission signals via a transmission line in the transmission interface format. A signal receiving section receives the transmission signals. A signal restoring section restores the multiplexed signal by constructing the divided signals on the basis of the guarantee information.

Transmission system

A read address from a memory and a write address to the memory are transmitted from a VT pointer circuit on an active side to a VT pointer circuit on a standby side in order to eliminate a difference between pointer values of the VT pointer circuits on the active and the standby sides, which is caused by a difference between the phases of the read address from the memory and the write address to the memory of the VT pointer circuits on the active and the standby sides, and the read and the write addresses on the standby side are overwritten with the transmitted address values. As a result, the address values can be made to match both on the active and the standby sides, and also the pointer values can be made to match.

Momentary-disconnection-free switching device

A plug-in card for an optical transmission apparatus includes a J1generating unit. The J1 generating unit sends information on on-use side J1 data to a plug-in card at a spare side in a redundant structure when the plug-in card operates as an on-use side plug-in card. The J1 generating unit receives information on on-use side J1 data from a plug-in card at the on-use side when the plug-in card operates as a spare side plug-in card. Based on the information, the J1 generating unit matches spare side J1 data to the on-use side J1 data. The plug-in card also includes a B3 byte calculating unit that operates in a similar way as the J1 generating unit does in processing B3 byte data.

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Kawasaki, Japan

Hideki Matsui