Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Yamaichi Electronics Co., Ltd.

Hideki Kawai

Masaru Fujii

Kiyoto Ohta

Masahiko Sakagami

Toshiyasu Ito

Yutaka Nakamura

Hiroshi Sakurai

Tsutomu Sekibe

Tomoaki Izumi

Takashi Torii

Masaaki Oya

Tatsuhiro Hosokawa

Shoichi Tsujita

Kazutaka Taguchi

Yoshikazu Maeyama

Toshio Nishimoto

The connector housingis formed with a pair of guide groovesand a pair of side walls. The guide groovessupport the both side edges of the upper body portionof the thick first cardand also the both side edges of the card bodyof the thin second cardand guide these cards as they are inserted or extracted. The side wallsdefine, below a space between the paired guide grooves, a space in which to accommodate the lower body portionof the first card. This construction ensures that, whichever of the first and second cards is inserted, the elastic displacements of the contact terminalsof a card connectorremain the same, allowing the card to be electrically connected stably.

Card connector

Even when an S-PCI busrequests transfer while a P-PCI busis executing burst transfer, assert of a TRDY# signal for data transfer of the P-PCI side is delayed so that next data transfer of the P-PCI side is completed within 8 clock cycles since the TRDY# signal for data transfer of the P-PCI side is asserted.

Data transfer control device

A semiconductor memory card is provided that includes: a data storing part; a control part writing and reading data into and from the data storing part; an interface circuit; and a plurality of input and output terminals, wherein data input and output terminal pairs are each allotted to a different terminal pair so that no terminal pair acts as both the data input terminal pair and the data output terminal pair, and a clock input terminal and a clock output terminal are included. The interface circuit receives an input clock from the clock input terminal, receives a complementary input data pair synchronized with the input clock from the data input terminal pair, outputs a complementary output data pair from the data output terminal pair, and outputs an output clock synchronized with the complementary output data pair from the clock output terminal.

Semiconductor memory card, method of controlling the same and interface apparatus for semiconductor memory card

A communication interface of the present invention includes a clock signal line, a first signal line, a second signal line and one or more data signal lines as communication signal lines between a master system and a slave system.

Communication interface having a master activating/deactivating a first signal with a clock signal after a predetermined time after a slave activating/deactivating the first signal

This invention is realized, in sum, by providing at least one reset input terminal, aside from a reset input terminal to which a request end signal is supplied, to output stage RS flip-flops of plural latch circuits to which plural request signals are supplied respectively. The signal of a first output terminal of the output stage RS flip-flop of a specified latch circuit of the plural latch circuits is supplied to a reset input terminal of the output stage RS flip-flop of the other latch circuit and a delay circuit is connected between a second output terminal and the other reset input terminal of the output stage RS flip-flops of each latch circuit. Accordingly, if plural request signals are supplied at substantially the same time, the competition of these request signals may be settled. Besides, by setting the delay time of each delay circuit longer than the time required from the supply of the signal to the set input terminal of the corresponding output stage RS flip-flop until the signal is latched in the output terminal, even if pulsive signals are supplied to the output stage RS flip-flops, oscillation of the output stage RS flip-flops may be prevented.

Arbiter circuit using plural-reset RS flip-flops

In a memory device, a shift-register comprises a plurality of stages for transferring sequentially a pair of signals which have mutually opposite phases. Each stage has a comparator circuit which compares the pair of signals and generates a pair of fixed voltage signals. By this construction, high-speed operation of the memory device, low power consumptions, and high-capacity load driving are achieved.

Memory device using shift-register

In a semiconductor integrated circuit device having at least one shift register, a plurality of 5 stages of the shift register are electrically connected in series, the 1st stage of said shift register is located in the closest position to the data input terminal, and other succeeding stages are sequentially and straightly located at intervals; the chain of the stages is folded at a particular stage, and further succeeding stages are sequentially and straightly located at intervals so as to fill in the spaces between the other stages, thus, the unbalance of the load capacitance between said stages and the functional unbalance between the shift registers can be minimized.

Semiconductor integrated circuit device including shift register having

In a semiconductor memory device, a memory cell array is separated into at least two portions on a substrate, and a serial memory element, such as a shift register, and control signal lines are collectively disposed between the two memory cell array portions, and by this arrangement, the length of the control signal lines and data lines can be minimized so that the stray or parasitic capacitance is reduced, and a higher speed and stable operation of the device is thereby realized.

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Nara, Japan

Hideki Kawai